coolrunner2.v

Xilinx Ise 官方源代码盘 第四章

input I2;
input I3;
input I4;
endmodule
module NOR5B3(O, I0, I1, I2, I3, I4) /* synthesis syn_black_box  */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
module NOR5B4(O, I0, I1, I2, I3, I4) /* synthesis syn_black_box  */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
module NOR5B5(O, I0, I1, I2, I3, I4) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
module NOR6(O, I0, I1, I2, I3, I4, I5) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
input I5;
endmodule
module NOR7(O, I0, I1, I2, I3, I4, I5, I6) /* synthesis syn_black_box  */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
input I5;
input I6;
endmodule
module NOR8(O, I0, I1, I2, I3, I4, I5, I6, I7) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
input I5;
input I6;
input I7;
endmodule
module NOR9(O, I0, I1, I2, I3, I4, I5, I6, I7, I8) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
input I5;
input I6;
input I7;
input I8;
endmodule
module OBUF(O, I) /* synthesis syn_black_box */;
output O /* synthesis .ispad = 1 */;
input I;
endmodule
module OBUFE(O, E, I) /* synthesis syn_black_box */;
output O /* synthesis .ispad = 1 syn_tristate=1*/;
input E;
input I;
endmodule
module OBUFT(O, I, T) /* synthesis syn_black_box */;
output O /* synthesis .ispad = 1 syn_tristate = 1 */;
input I;
input T;
endmodule
module OR2(O, I0, I1) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
endmodule
module OR2B1(O, I0, I1) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
endmodule
module OR2B2(O, I0, I1) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
endmodule
module OR3(O, I0, I1, I2) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
endmodule
module OR3B1(O, I0, I1, I2) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
endmodule
module OR3B2(O, I0, I1, I2) /* synthesis syn_black_box  */;
output O;
input I0;
input I1;
input I2;
endmodule
module OR3B3(O, I0, I1, I2) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
endmodule
module OR4(O, I0, I1, I2, I3) /* synthesis syn_black_box  */;
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
module OR4B1(O, I0, I1, I2, I3) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
module OR4B2(O, I0, I1, I2, I3) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
module OR4B3(O, I0, I1, I2, I3) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
module OR4B4(O, I0, I1, I2, I3) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
module OR5(O, I0, I1, I2, I3, I4) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
module OR5B1(O, I0, I1, I2, I3, I4) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
module OR5B2(O, I0, I1, I2, I3, I4) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
module OR5B3(O, I0, I1, I2, I3, I4) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
module OR5B4(O, I0, I1, I2, I3, I4) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
module OR5B5(O, I0, I1, I2, I3, I4) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
module OR6(O, I0, I1, I2, I3, I4, I5) /* synthesis syn_black_box  */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
input I5;
endmodule
module OR7(O, I0, I1, I2, I3, I4, I5, I6) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
input I5;
input I6;
endmodule
module OR8(O, I0, I1, I2, I3, I4, I5, I6, I7) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
input I5;
input I6;
input I7;
endmodule
module OR9(O, I0, I1, I2, I3, I4, I5, I6, I7, I8) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
input I5;
input I6;
input I7;
input I8;
endmodule
module VCC(P) /* synthesis syn_black_box syn_noprune=1 */;
output P;
endmodule
module XNOR2(O, I0, I1) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
endmodule
module XNOR3(O, I0, I1, I2) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
endmodule
module XNOR4(O, I0, I1, I2, I3) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
module XOR2(O, I0, I1) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
endmodule
module XOR3(O, I0, I1, I2) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
endmodule
module XOR4(O, I0, I1, I2, I3) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
module XOR5(O,I0,I1,I2,I3,I4) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
module XOR6(O,I0,I1,I2,I3,I4,I5) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
input I5;
endmodule
module XOR7(O,I0,I1,I2,I3,I4,I5,I6) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
input I5;
input I6;
endmodule
module XOR8(O,I0,I1,I2,I3,I4,I5,I6,I7) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
input I5;
input I6;
input I7;
endmodule
module CLK_DIV2(CLKIN,CLKDV) /* synthesis syn_black_box */;
input CLKIN;
output CLKDV;
endmodule
module CLK_DIV4(CLKIN,CLKDV) /* synthesis syn_black_box */;
input CLKIN;
output CLKDV;
endmodule
module CLK_DIV6(CLKIN,CLKDV) /* synthesis syn_black_box */;
input CLKIN;
output CLKDV;
endmodule
module CLK_DIV8(CLKIN,CLKDV) /* synthesis syn_black_box */;
input CLKIN;
output CLKDV;
endmodule
module CLK_DIV10(CLKIN,CLKDV) /* synthesis syn_black_box */;
input CLKIN;
output CLKDV;
endmodule
module CLK_DIV12(CLKIN,CLKDV) /* synthesis syn_black_box */;
input CLKIN;
output CLKDV;
endmodule
module CLK_DIV14(CLKIN,CLKDV) /* synthesis syn_black_box */;
input CLKIN;
output CLKDV;
endmodule
module CLK_DIV16(CLKIN,CLKDV) /* synthesis syn_black_box */;
input CLKIN;
output CLKDV;
endmodule
module CLK_DIV2R(CLKIN,CLKDV) /* synthesis syn_black_box */;
input CLKIN;
output CLKDV;
endmodule
module CLK_DIV4R(CLKIN,CLKDV) /* synthesis syn_black_box */;
input CLKIN;
output CLKDV;
endmodule
module CLK_DIV6R(CLKIN,CLKDV) /* synthesis syn_black_box */;
input CLKIN;
output CLKDV;
endmodule
module CLK_DIV8R(CLKIN,CLKDV) /* synthesis syn_black_box */;
input CLKIN;
output CLKDV;
endmodule
module CLK_DIV10R(CLKIN,CLKDV) /* synthesis syn_black_box */;
input CLKIN;
output CLKDV;
endmodule
module CLK_DIV12R(CLKIN,CLKDV) /* synthesis syn_black_box */;
input CLKIN;
output CLKDV;
endmodule
module CLK_DIV14R(CLKIN,CLKDV) /* synthesis syn_black_box */;
input CLKIN;
output CLKDV;
endmodule
module CLK_DIV16R(CLKIN,CLKDV) /* synthesis syn_black_box */;
input CLKIN;
output CLKDV;
endmodule
module CLK_DIV2RSD(CLKIN,CLKDV) /* synthesis syn_black_box */;
input CLKIN;
output CLKDV;
endmodule
module CLK_DIV4RSD(CLKIN,CLKDV) /* synthesis syn_black_box */;
input CLKIN;
output CLKDV;
endmodule
module CLK_DIV6RSD(CLKIN,CLKDV) /* synthesis syn_black_box */;
input CLKIN;
output CLKDV;
endmodule
module CLK_DIV8RSD(CLKIN,CLKDV) /* synthesis syn_black_box */;
input CLKIN;
output CLKDV;
endmodule
module CLK_DIV10RSD(CLKIN,CLKDV) /* synthesis syn_black_box */;
input CLKIN;
output CLKDV;
endmodule
module CLK_DIV12RSD(CLKIN,CLKDV) /* synthesis syn_black_box */;
input CLKIN;
output CLKDV;
endmodule
module CLK_DIV14RSD(CLKIN,CLKDV) /* synthesis syn_black_box */;
input CLKIN;
output CLKDV;
endmodule
module CLK_DIV16RSD(CLKIN,CLKDV) /* synthesis syn_black_box */;
input CLKIN;
output CLKDV;
endmodule
module CLK_DIV2SD(CLKIN,CLKDV) /* synthesis syn_black_box */;
input CLKIN;
output CLKDV;
endmodule
module CLK_DIV4SD(CLKIN,CLKDV) /* synthesis syn_black_box */;
input CLKIN;
output CLKDV;
endmodule
module CLK_DIV6SD(CLKIN,CLKDV) /* synthesis syn_black_box */;
input CLKIN;
output CLKDV;
endmodule
module CLK_DIV8SD(CLKIN,CLKDV) /* synthesis syn_black_box */;
input CLKIN;
output CLKDV;
endmodule
module CLK_DIV10SD(CLKIN,CLKDV) /* synthesis syn_black_box */;
input CLKIN;
output CLKDV;
endmodule
module CLK_DIV12SD(CLKIN,CLKDV) /* synthesis syn_black_box */;
input CLKIN;
output CLKDV;
endmodule
module CLK_DIV14SD(CLKIN,CLKDV) /* synthesis syn_black_box */;
input CLKIN;
output CLKDV;
endmodule
module CLK_DIV16SD(CLKIN,CLKDV) /* synthesis syn_black_box */;
input CLKIN;
output CLKDV;
endmodule
module FDDCE(D,CE,C,CLR,Q) /* synthesis syn_black_box */;
input D;
input CE;
input C;
input CLR;
output Q;
endmodule
module FDDCP(PRE,D,C,CLR,Q) /* synthesis syn_black_box */;
input PRE;
input D;
input C;
input CLR;
output Q;
endmodule
module FDDCPE(PRE,D,CE,C,CLR,Q) /* synthesis syn_black_box */;
input PRE;
input D;
input CE;
input C;
input CLR;
output Q;
endmodule
module FDDP(PRE,D,C,Q) /* synthesis syn_black_box */;
input PRE;
input D;
input C;
output Q;
endmodule
module FDDPE(PRE,D,CE,C,Q) /* synthesis syn_black_box */;
input PRE;
input D;
input CE;
input C;
output Q;
endmodule