xc4000.v

Xilinx Ise 官方源代码盘 第四章

module OFDT_MS (O, C, D, T)	/* synthesis xc_padmacro=1 */;
    output   O /* synthesis .ispad=1 */;
    input    C, D, T;
	OFDTX oft1(O, C, 1'b1, D, T) /* synthesis xc_props="MEDSLOW"*/;
endmodule
module OFDT_U (O, C, D, T)	/* synthesis xc_padmacro=1 */;
    output   O /* synthesis .ispad=1 */;
    input    C, D, T;
	OFDTX oft1(O, C, 1'b1, D, T) /* synthesis xc_props="UNBONDED"*/;
endmodule
module OFDT_INT (O, C, D, T)	/* synthesis xc_padmacro=1 */;
    output   O /* synthesis .ispad=1 */;
    input    C, D, T;
	OFDTX oft1(O, C, 1'b1, D, T);
endmodule
module OFDTI (O, C, D, T)	/* synthesis xc_padmacro=1 */;
    output   O /* synthesis .ispad=1 */;
    input    C, D, T;
	OFDTXI ofti1(O, C, 1'b1, D, T);
endmodule
module OFDTI_F (O, C, D, T)	/* synthesis xc_padmacro=1 */;
    output   O /* synthesis .ispad=1 */;
    input    C, D, T;
	OFDTXI ofti1(O, C, 1'b1, D, T) /* synthesis xc_props="FAST"*/;
endmodule
module OFDTI_S (O, C, D, T) 	/* synthesis xc_padmacro=1 */;
    output   O /* synthesis .ispad=1 */;
    input    C, D, T;
	OFDTXI ofti1(O, C, 1'b1, D, T)/* synthesis xc_props="SLOW"*/;
endmodule
module OFDTI_U (O, C, D, T)	/* synthesis xc_padmacro=1 */;
    output   O /* synthesis .ispad=1 */;
    input    C, D, T;
	OFDTXI ofti1(O, C, 1'b1, D, T) /* synthesis xc_props="UNBONDED"*/;
endmodule
module OFDTI_MF (O, C, D, T)	/* synthesis xc_padmacro=1 */;
    output   O /* synthesis .ispad=1 */;
    input    C, D, T;
	OFDTXI ofti1(O, C, 1'b1, D, T) /* synthesis xc_props="MEDFAST"*/;
endmodule
module OFDTI_MS (O, C, D, T)	/* synthesis xc_padmacro=1 */;
    output   O /* synthesis .ispad=1 */;
    input    C, D, T;
	OFDTXI ofti1(O, C, 1'b1, D, T)  /* synthesis xc_props="MEDSLOW"*/;
endmodule
module OFDTI_INT (O, C, D, T)	/* synthesis xc_padmacro=1 */;
    output   O /* synthesis .ispad=1 */;
    input    C, D, T;
	OFDTXI ofti1(O, C, 1'b1, D, T);
endmodule
module OFDTX (O, C, CE, D, T) /* synthesis syn_black_box */;
    output   O /* synthesis .ispad=1 syn_tristate=1 */;
    input    C, CE, D, T;
endmodule
module OFDTXI (O, C, CE, D, T) /* synthesis syn_black_box */;
    output   O /* synthesis .ispad=1 syn_tristate=1 */;
    input    C, CE, D, T;
endmodule
module OFDX ( Q, C, CE, D) /* synthesis syn_black_box */;
    output   Q /* synthesis .ispad=1 */;
	input    C;
	input    CE;
	input    D;
endmodule
module OFDXI ( Q, C, CE, D) /* synthesis syn_black_box */;
    output   Q /* synthesis .ispad=1 */;
	input    C;
	input    CE;
	input    D;
endmodule
module OR2 (O, I0, I1) /* synthesis syn_black_box xc_alias="OR"*/;
    output   O;
    input    I0, I1;
endmodule
module OR3 (O, I0, I1, I2) /* synthesis syn_black_box xc_alias="OR" */;
    output   O;
    input    I0, I1, I2;
endmodule
module OR4 (O, I0, I1, I2, I3) /* synthesis syn_black_box xc_alias="OR" */;
    output   O;
    input    I0, I1, I2, I3;
endmodule
module OR5 (O, I0, I1, I2, I3, I4) /* synthesis syn_black_box xc_alias="OR" */;
    output   O;
    input    I0, I1, I2, I3, I4;
endmodule
module OSC4 (F8M, F500K, F16K, F490, F15) /* synthesis syn_black_box .noprune=1 */;
  output     F8M, F500K, F16K, F490, F15;
endmodule
module PULLDOWN(O) /* synthesis syn_black_box .noprune=1 */;
output O /* synthesis syn_not_a_driver=1 */;
endmodule
module PULLDOWN1 (O) /* synthesis .noprune=1 */;
output O;
 PULLDOWN p(O);
endmodule
module PULLUP(O) /* synthesis syn_black_box .noprune=1 */;
output O /* synthesis syn_not_a_driver=1 */;
endmodule
module PULLUP1 (O) /* synthesis .noprune=1 */;
output O;
 PULLUP p(O);
endmodule
// Only applicable for XC4000E, XC4000X families
module RAM16X1 (O, A0, A1, A2, A3, D, WE) /* synthesis syn_black_box */;
parameter INIT = 16'h0000;
  output   O;
  input    A0, A1, A2, A3, D, WE;
endmodule
// Only applicable for XC4000E, XC4000X families
module RAM32X1 (O, A0, A1, A2, A3, A4, D, WE) /* synthesis syn_black_box */;
parameter INIT = 32'h00000000;
  output   O;
  input    A0, A1, A2, A3, A4, D, WE;
endmodule
module RAM16X1D (A3,A2,A1,A0,DPRA3,DPRA2,DPRA1,DPRA0,D,DPO,SPO,WE,WCLK ); // synthesis syn_black_box xc_alias="RAMD"
parameter INIT = 16'h0000;
input D,A3,A2,A1,A0,DPRA3,DPRA2,DPRA1,DPRA0,WE,WCLK;
output DPO,SPO;
endmodule
module RDBK(DATA, RIP, TRIG) /* synthesis syn_black_box */;
  output DATA, RIP;
  input  TRIG;
endmodule
module READBACK(DATA, RIP, CLK, TRIG)/* synthesis .noprune=1 */;
  output DATA, RIP;
  input  CLK, TRIG;
  RDBK r1(.DATA(DATA), .RIP(RIP), .TRIG(TRIG));
  RDCLK r2(.I(CLK));
endmodule
module RDCLK(I) /* synthesis syn_black_box .noprune=1 */;
  input I;
endmodule
module ROM16X1 (O, A0, A1, A2, A3) /* synthesis syn_black_box */;
parameter INIT = 16'h0000;
  output   O;
  input    A0, A1, A2, A3;
endmodule
module ROM32X1 (O, A0, A1, A2, A3, A4) /* synthesis syn_black_box */;
parameter INIT = 32'h00000000;
  output   O;
  input    A0, A1, A2, A3, A4;
endmodule
module STARTUP_CLK (CLK, Q2, Q3, Q1Q4, DONEIN) 
/* synthesis syn_black_box .noprune=1 xc_alias="STARTUP"*/ ;
    output   Q2, Q3, Q1Q4, DONEIN;
    input  CLK;
endmodule
module STARTUP_GSR (GSR) /* synthesis syn_black_box .noprune=1 */;
    input  GSR;
endmodule
module STARTUP_GTS (GTS) /* synthesis syn_black_box .noprune=1 xc_alias="STARTUP"*/;
    input  GTS;
endmodule
module STARTUP_ALL(Q2,Q3,Q1Q4,DONEIN, GSR,GTS,CLK)
/* synthesis syn_black_box .noprune=1 xc_alias="STARTUP" */ ;
output Q2,Q3, Q1Q4, DONEIN;
input GSR /* synthesis syn_defaultvalue=0 */,
      GTS /* synthesis syn_defaultvalue=0 */,
      CLK /* synthesis syn_defaultvalue=0 */;
endmodule
module STARTUP(Q2,Q3,Q1Q4,DONEIN, GSR,GTS,CLK)
/* synthesis .noprune=1 */;
output Q2,Q3, Q1Q4, DONEIN;
input GSR /* synthesis syn_defaultvalue=0 */,
      GTS /* synthesis syn_defaultvalue=0 */,
      CLK /* synthesis syn_defaultvalue=0 */;
STARTUP_GSR gsr( GSR );
STARTUP_GTS gts( GTS );
STARTUP_CLK clk(.CLK(CLK), .Q2(Q2), .Q3(Q3), .Q1Q4(Q1Q4), .DONEIN(DONEIN));
endmodule
module WAND1 (O, I) /* synthesis syn_black_box xc_alias="WAND"*/;
  output   O /* synthesis syn_tristate=1 */;
  input    I;
endmodule
module DECODE1_IO (O, I) /* synthesis xc_props="DECODE"*/;
  inout   O;
  input    I;
  WAND1 i1 (O, I);
endmodule
module DECODE1_INT (O, I) /* synthesis xc_props="DECODE"*/;
  inout   O;
  input    I;
  WAND1 i1 (O, I);
endmodule
module DECODE4 (O, A) /* synthesis xc_props="DECODE" */;
  inout O;
  input [3:0] A;
  WAND1 i0 (O, A[0]);
  WAND1 i1 (O, A[1]);
  WAND1 i2 (O, A[2]);
  WAND1 i3 (O, A[3]);
endmodule
module DECODE8 (O, A) /* synthesis xc_props="DECODE" */;
  inout O;
  input [7:0] A;
  WAND1 i0 (O, A[0]);
  WAND1 i1 (O, A[1]);
  WAND1 i2 (O, A[2]);
  WAND1 i3 (O, A[3]);
  WAND1 i4 (O, A[4]);
  WAND1 i5 (O, A[5]);
  WAND1 i6 (O, A[6]);
  WAND1 i7 (O, A[7]);
endmodule
module DECODE16 (O, A) /* synthesis xc_props="DECODE" */;
  inout O;
  input [15:0] A;
  WAND1 i0 (O, A[0]);
  WAND1 i1 (O, A[1]);
  WAND1 i2 (O, A[2]);
  WAND1 i3 (O, A[3]);
  WAND1 i4 (O, A[4]);
  WAND1 i5 (O, A[5]);
  WAND1 i6 (O, A[6]);
  WAND1 i7 (O, A[7]);
  WAND1 i8 (O, A[8]);
  WAND1 i9 (O, A[9]);
  WAND1 i10 (O, A[10]);
  WAND1 i11 (O, A[11]);
  WAND1 i12 (O, A[12]);
  WAND1 i13 (O, A[13]);
  WAND1 i14 (O, A[14]);
  WAND1 i15 (O, A[15]);
endmodule
module WOR2AND (O, I0, I1) /* synthesis syn_black_box xc_alias="WORAND"*/;
  output   O;
  input    I0, I1;
endmodule
module XGND(GROUND) /* synthesis syn_black_box .noprune=1 xc_alias="GND"*/;
  output GROUND;
endmodule
module XNOR2 (O, I0, I1) /* synthesis syn_black_box xc_alias="XNOR"*/;
    output   O;
    input    I0, I1;
endmodule
module XNOR3 (O, I0, I1, I2) /* synthesis syn_black_box xc_alias=XNOR"*/;
    output   O;
    input    I0, I1, I2;
endmodule
module XNOR4 (O, I0, I1, I2, I3) /* synthesis syn_black_box xc_alias="XNOR"*/;
    output   O;
    input    I0, I1, I2, I3;
endmodule
module XNOR5 (O, I0, I1, I2, I3, I4) /* synthesis syn_black_box xc_alias="XNOR"*/;
    output   O;
    input    I0, I1, I2, I3, I4;
endmodule
module XOR2 (O, I0, I1) /* synthesis syn_black_box xc_alias="XOR"*/;
    output   O;
    input    I0, I1;
endmodule
module XOR3 (O, I0, I1, I2) /* synthesis syn_black_box xc_alias="XOR"*/;
    output   O;
    input    I0, I1, I2;
endmodule
module XOR4 (O, I0, I1, I2, I3) /* synthesis syn_black_box xc_alias="XOR"*/;
    output   O;
    input    I0, I1, I2, I3;
endmodule
module XOR5 (O, I0, I1, I2, I3, I4) /* synthesis syn_black_box xc_alias="XOR"*/;
    output   O;
    input    I0, I1, I2, I3, I4;
endmodule
module XVCC(POWER) /* synthesis syn_black_box .noprune=1 xc_alias="VCC"*/;
  output POWER;
endmodule
module FDP_1 (Q, C, D, PRE) ;
    output   Q;
    input    C, D, PRE;
	FDPE f1(.Q(Q), .C(~C), .CE(1'b1), .D(D), .PRE(PRE));
endmodule
module FDPE_1 (Q, C, CE, D, PRE);
    output   Q;
    input    C, CE, D, PRE;
	FDPE f1(.Q(Q), .C(~C), .CE(CE), .D(D), .PRE(PRE));
endmodule
module IFD_1 (Q, C, D)	/* synthesis xc_padmacro=1 */;
    output   Q;
    input    C;
    input    D /* synthesis .ispad=1 */;
	IFDX if1 (.Q(Q), .C(~C), .CE(1'b1), .D(D));
endmodule
module IFDX_F (Q, C, D, CE)	/* synthesis xc_padmacro=1 */;
    output   Q;
    input    C, CE;
    input    D /* synthesis .ispad=1 */;
	IFDX if1 (.Q(Q), .C(C), .CE(CE), .D(D)) /* synthesis xc_props="NODELAY"*/;
endmodule
module IFDX_1 (Q, C, D, CE)	/* synthesis xc_padmacro=1 */;
    output   Q;
    input    C, CE;
    input    D /* synthesis .ispad=1 */;
	IFDX if1 (.Q(Q), .C(~C), .CE(CE), .D(D));
endmodule
module IFDXI_F (Q, CE, C, D)	/* synthesis xc_padmacro=1 */;
    output   Q;
    input    C, CE;
    input D /* synthesis .ispad=1 */;
	IFDXI ifi1 (.Q(Q), .C(C), .CE(CE), .D(D)) /* synthesis xc_props="NODELAY"*/;
endmodule
module IFDXI_1 (Q, CE, C, D)	/* synthesis xc_padmacro=1 */;
    output   Q;
    input    C, CE;
    input D /* synthesis .ispad=1 */;
	IFDXI ifi1 (.Q(Q), .C(~C), .CE(CE), .D(D));
endmodule
module ILD (Q, D, G)	/* synthesis xc_padmacro=1 */;
    output   Q;
    input    G;
    input    D /* synthesis .ispad=1 */;
	ILDX_1 il1( .Q(Q), .D(D), .G(~G), .GE(1'b1) );
endmodule
module ILDX (Q, D, GE, G)	/* synthesis xc_padmacro=1 */;
    output   Q;
    input    G, GE;
    input    D /* synthesis .ispad=1 */;
	ILDX_1 il1( .Q(Q), .D(D), .G(~G), .GE(GE) );
endmodule
module ILDXI (Q, D, GE, G)	/* synthesis xc_padmacro=1 */;
    output   Q;
    input    G, GE;
    input    D /* synthesis .ispad=1 */;
	ILDXI_1 ili1(.Q(Q), .D(D), .G(~G), .GE(GE));
endmodule
module OFD_1 (Q, C, D)	/* synthesis xc_padmacro=1 */;
    output   Q /* synthesis .ispad=1 */;
    input    C, D;
	OFDX of1(.Q(Q), .C(~C), .CE(1'b1), .D(D));
endmodule
module OFDT_1 (O, C, D, T)	/* synthesis xc_padmacro=1 */;
    output   O /* synthesis .ispad=1 */;
    input    C, D, T;
	OFDTX of1 (.O(O), .C(~C), .CE(1'b1), .D(D), .T(T));
endmodule
module OFDTX_F (O, CE, C, D, T)	/* synthesis xc_padmacro=1 */;
    output   O /* synthesis .ispad=1 */;
    input    C, D, CE, T;
	OFDTX of1 (.O(O), .C(C), .CE(CE), .D(D), .T(T))  /* synthesis xc_props="FAST"*/ ;
endmodule
module OFDTX_1 (O, C, CE, D, T)	/* synthesis xc_padmacro=1 */;
    output   O /* synthesis .ispad=1 */;
    input    C, CE, D, T;
	OFDTX of1 (.O(O), .C(~C), .CE(CE), .D(D), .T(T));
endmodule
module OFDTXI_F (O, CE, C, D, T)	/* synthesis xc_padmacro=1 */;
    output   O /* synthesis .ispad=1 */;
    input    C, D, CE, T;
	OFDTXI ofi1 (.O(O), .C(C), .CE(CE), .D(D), .T(T)) /* synthesis xc_props="FAST"*/;
endmodule
module OFDTXI_1 (O, C, CE, D, T)	/* synthesis xc_padmacro=1 */;
    output   O /* synthesis .ispad=1 */;
    input    C, CE, D, T;
	OFDTXI ofi1 (.O(O), .C(~C), .CE(CE), .D(D), .T(T));
endmodule
module OFDX_F (Q, CE, C, D)	/* synthesis xc_padmacro=1 */;
    output   Q /* synthesis .ispad=1 */;
    input    C, D, CE;
	OFDX of1(.Q(Q), .CE(CE), .C(C), .D(D)) /* synthesis xc_props="FAST"*/;
endmodule
module OFDX_1 (Q, CE, C, D)	/* synthesis xc_padmacro=1 */;
    output   Q /* synthesis .ispad=1 */;
    input    C, D, CE;
	OFDX of1(.Q(Q), .CE(CE), .C(~C), .D(D));
endmodule
module OFDXI_F (Q, CE, C, D)	/* synthesis xc_padmacro=1 */;
    output   Q /* synthesis .ispad=1 */;
    input    C, D, CE ;
	OFDXI ofi1(.Q(Q), .CE(CE), .C(C), .D(D)) /* synthesis xc_props="FAST"*/;
endmodule
module OFDXI_1 (Q, CE, C, D)	/* synthesis xc_padmacro=1 */;
    output   Q /* synthesis .ispad=1 */;
    input    C, D, CE ;
	OFDXI ofi1(.Q(Q), .CE(CE), .C(~C), .D(D));
endmodule
module RAM16X1S (O,A3,A2,A1,A0,D,WE,WCLK ); // synthesis syn_black_box
parameter INIT = 16'h0000;
input D,A3,A2,A1,A0,WE,WCLK;
output O;
endmodule
module RAM32X1S (O,A4,A3,A2,A1,A0,D,WE,WCLK ); // synthesis syn_black_box
parameter INIT = 32'h00000000;
input D,A4,A3,A2,A1,A0,WE,WCLK;
output O;
endmodule