📄 xc4000.v
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input D /* synthesis .ispad=1 */;
ILDXI_1 ili1(Q, D, G, 1'b1);
endmodule
module ILDI_1F (Q, D, G) /* synthesis xc_padmacro=1 xc_props="NODELAY"*/;
output Q;
input G;
input D /* synthesis .ispad=1 */;
ILDXI_1 ili1(Q, D, G, 1'b1);
endmodule
module ILDI_1U (Q, D, G) /* synthesis xc_padmacro=1 xc_props="UNBONDED"*/;
output Q;
input G;
input D /* synthesis .ispad=1 */;
ILDXI_1 ili1(Q, D, G, 1'b1);
endmodule
module ILDI_1_INT (Q, D, G) /* synthesis xc_padmacro=1 */;
output Q;
input G;
input D /* synthesis .ispad=1 */;
ILDXI_1 ili1(Q, D, G, 1'b1);
endmodule
module ILDX_1 (Q, D, G, GE) /* synthesis syn_black_box */;
output Q;
input G;
input GE;
input D /* synthesis .ispad=1 */;
endmodule
module ILDXI_1 (Q, D, G, GE) /* synthesis syn_black_box */;
output Q;
input G;
input GE;
input D /* synthesis .ispad=1 */;
endmodule
// For Spartan-xl and 4000X only
module ILFFX (Q, D, GF, CE, C) /* synthesis syn_black_box */;
output Q;
input D /* synthesis .ispad = 1 */;
input GF;
input CE;
input C;
endmodule
// For Spartan-xl and 4000X only
module ILFFXI (Q, D, GF, CE, C) /* synthesis syn_black_box */;
output Q;
input D /* synthesis .ispad = 1 */;
input GF;
input CE;
input C;
endmodule
// For Spartan-xl and 4000X only
module ILFLX_1 (Q, D, GF, GE, G) /* synthesis syn_black_box */;
output Q;
input D /* synthesis .ispad = 1 */;
input GF;
input GE;
input G;
endmodule
// For Spartan-xl and 4000X only
module ILFLXI_1 (Q, D, GF, GE, G) /* synthesis syn_black_box */;
output Q;
input D /* synthesis .ispad = 1 */;
input GF;
input GE;
input G;
endmodule
// For Spartan-xl and 4000X only
module ILFLX (Q, D, GF, GE, G) /* synthesis xc_padmacro=1 */;
output Q;
input D /* synthesis .ispad = 1 */;
input GF;
input GE;
input G;
ILFLX_1 ilflx1(.Q(Q), .D(D), .GF(GF), .GE(GE), .G(~G));
endmodule
module LDCE_1 (Q, CLR, D, G, GE) /* synthesis syn_black_box */;
output Q;
input CLR;
input D;
input G;
input GE;
endmodule
module INV (O, I) /* synthesis syn_black_box */;
output O;
input I;
endmodule
module NAND2 (O, I0, I1) /* synthesis syn_black_box xc_alias="NAND" */;
output O;
input I0, I1;
endmodule
module NAND3 (O, I0, I1, I2) /* synthesis syn_black_box xc_alias="NAND" */;
output O;
input I0, I1, I2;
endmodule
module NAND4 (O, I0, I1, I2, I3) /* synthesis syn_black_box xc_alias="NAND"*/;
output O;
input I0, I1, I2, I3;
endmodule
module NAND5 (O, I0, I1, I2, I3, I4) /* synthesis syn_black_box xc_alias="NAND"*/;
output O;
input I0, I1, I2, I3, I4;
endmodule
module NOR2 (O, I0, I1) /* synthesis syn_black_box xc_alias="NOR"*/;
output O;
input I0, I1;
endmodule
module NOR3 (O, I0, I1, I2) /* synthesis syn_black_box xc_alias="NOR" */;
output O;
input I0, I1, I2;
endmodule
module NOR4 (O, I0, I1, I2, I3) /* synthesis syn_black_box xc_alias="NOR" */;
output O;
input I0, I1, I2, I3;
endmodule
module NOR5 (O, I0, I1, I2, I3, I4) /* synthesis syn_black_box xc_alias="NOR"*/;
output O;
input I0, I1, I2, I3, I4;
endmodule
module OBUF (O, I) /* synthesis syn_black_box */;
output O /* synthesis .ispad=1 */;
input I;
endmodule
module OBUF_F (O, I) /* synthesis syn_black_box xc_alias="OBUF" xc_props="FAST"*/;
output O /* synthesis .ispad=1 */;
input I;
endmodule
module OBUF_S (O, I) /* synthesis syn_black_box xc_alias="OBUF" xc_props="SLOW"*/;
output O /* synthesis .ispad=1 */;
input I;
endmodule
module OBUF_U (O, I) /* synthesis syn_black_box xc_alias="OBUF" xc_props="UNBONDED"*/;
output O /* synthesis .ispad=1 */;
input I;
endmodule
module OBUF_MF (O, I) /* synthesis syn_black_box xc_alias="OBUF" xc_props="MEDFAST"*/;
output O /* synthesis .ispad=1 */;
input I;
endmodule
module OBUF_MS (O, I) /* synthesis syn_black_box xc_alias="OBUF" xc_props="MEDSLOW"*/;
output O /* synthesis .ispad=1 */;
input I;
endmodule
module OBUF_CMOSCAP (O, I) /* synthesis syn_black_box xc_alias="OBUF" xc_props="CMOS, CAP"*/;
output O /* synthesis .ispad=1 */;
input I;
endmodule
module OBUF_CMOSRES (O, I) /* synthesis syn_black_box xc_alias="OBUF" xc_props="CMOS, RES"*/;
output O /* synthesis .ispad=1 */;
input I;
endmodule
module OBUF_TTLCAP (O, I) /* synthesis syn_black_box xc_alias="OBUF" xc_props="TTL, CAP"*/;
output O /* synthesis .ispad=1 */;
input I;
endmodule
module OBUF_TTLRES (O, I) /* synthesis syn_black_box xc_alias="OBUF" xc_props="TTL, RES"*/;
output O /* synthesis .ispad=1 */;
input I;
endmodule
module OBUF_INT (O, I) /* synthesis syn_black_box xc_alias="OBUF" */;
output O /* synthesis .ispad=1 */;
input I;
endmodule
module OBUFT (O, I, T) /* synthesis syn_black_box */;
output O /* synthesis .ispad=1 syn_tristate=1 */;
input I, T;
endmodule
module OBUFT_F (O, I, T) /* synthesis syn_black_box xc_alias="OBUFT" xc_props="FAST"*/;
output O /* synthesis .ispad=1 syn_tristate=1 */;
input I, T;
endmodule
module IOBUF_N_F (O, IO, I, T);
output O;
inout IO /* synthesis .ispad=1 */;
input I,T;
OBUFT_F i0 (IO, I, T);
IBUF i1 (O, IO);
endmodule
module OBUFT_S (O, I, T) /* synthesis syn_black_box xc_alias="OBUFT" xc_props="SLOW"*/;
output O /* synthesis .ispad=1 syn_tristate=1 */;
input I, T;
endmodule
module IOBUF (O, IO, I, T);
output O;
inout IO /* synthesis .ispad=1 */;
input I,T;
OBUFT_S i0 (IO, I, T);
IBUF i1 (O, IO);
endmodule
module IOBUF_N_S (O, IO, I, T);
output O;
inout IO /* synthesis .ispad=1 */;
input I,T;
OBUFT_S i0 (IO, I, T);
IBUF i1 (O, IO);
endmodule
module OBUFT_U (O, I, T) /* synthesis syn_black_box xc_alias="OBUFT" xc_props="UNBONDED"*/;
output O /* synthesis .ispad=1 syn_tristate=1 */;
input I, T;
endmodule
module OBUFT_MF (O, I, T) /* synthesis syn_black_box xc_alias="OBUFT" xc_props="MEDFAST"*/;
output O /* synthesis .ispad=1 syn_tristate=1 */;
input I, T;
endmodule
module IOBUF_N_MF (O, IO, I, T);
output O;
inout IO /* synthesis .ispad=1 */;
input I,T;
OBUFT_MF i0 (IO, I, T);
IBUF i1 (O, IO);
endmodule
module OBUFT_MS (O, I, T) /* synthesis syn_black_box xc_alias="OBUFT" xc_props="MEDSLOW"*/;
output O /* synthesis .ispad=1 syn_tristate=1 */;
input I, T;
endmodule
module IOBUF_N_MS (O, IO, I, T);
output O;
inout IO /* synthesis .ispad=1 */;
input I,T;
OBUFT_MS i0 (IO, I, T);
IBUF i1 (O, IO);
endmodule
module OBUFT_CMOSCAP (O, I, T) /* synthesis syn_black_box xc_alias="OBUFT" xc_props="CMOS, CAP"*/;
output O /* synthesis .ispad=1 syn_tristate=1 */;
input I, T;
endmodule
module IOBUF_CMOS_CMOSCAP (O, IO, I, T);
output O;
inout IO /* synthesis .ispad=1 */;
input I,T;
OBUFT_CMOSCAP i0 (IO, I, T);
IBUF_CMOS i1 (O, IO);
endmodule
module OBUFT_CMOSRES (O, I, T) /* synthesis syn_black_box xc_alias="OBUFT" xc_props="CMOS, RES"*/;
output O /* synthesis .ispad=1 syn_tristate=1 */;
input I, T;
endmodule
module IOBUF_CMOS_CMOSRES (O, IO, I, T);
output O;
inout IO /* synthesis .ispad=1 */;
input I,T;
OBUFT_CMOSRES i0 (IO, I, T);
IBUF_CMOS i1 (O, IO);
endmodule
module OBUFT_TTLCAP (O, I, T) /* synthesis syn_black_box xc_alias="OBUFT" xc_props="TTL, CAP"*/;
output O /* synthesis .ispad=1 syn_tristate=1 */;
input I, T;
endmodule
module IOBUF_TTL_TTLCAP (O, IO, I, T);
output O;
inout IO /* synthesis .ispad=1 */;
input I,T;
OBUFT_TTLCAP i0 (IO, I, T);
IBUF_TTL i1 (O, IO);
endmodule
module IOBUF_TTL_CMOSCAP (O, IO, I, T);
output O;
inout IO /* synthesis .ispad=1 */;
input I,T;
OBUFT_CMOSCAP i0 (IO, I, T);
IBUF_TTL i1 (O, IO);
endmodule
module OBUFT_TTLRES (O, I, T) /* synthesis syn_black_box xc_alias="OBUFT" xc_props="TTL, RES"*/;
output O /* synthesis .ispad=1 syn_tristate=1 */;
input I, T;
endmodule
module IOBUF_TTL_TTLRES (O, IO, I, T);
output O;
inout IO /* synthesis .ispad=1 */;
input I,T;
OBUFT_TTLRES i0 (IO, I, T);
IBUF_TTL i1 (O, IO);
endmodule
module IOBUF_TTL_CMOSRES (O, IO, I, T);
output O;
inout IO /* synthesis .ispad=1 */;
input I,T;
OBUFT_CMOSRES i0 (IO, I, T);
IBUF_TTL i1 (O, IO);
endmodule
module OBUFT_INT (O, I, T) /* synthesis syn_black_box xc_alias="OBUFT" */;
output O /* synthesis .ispad=1 syn_tristate=1 */;
input I, T;
endmodule
module OFD (Q, C, D) /* synthesis xc_padmacro=1 */;
output Q /* synthesis .ispad=1 */;
input C, D;
OFDX of1(Q, C, 1'b1, D);
endmodule
module OFD_F (Q, C, D) /* synthesis xc_padmacro=1 */;
output Q /* synthesis .ispad=1 */;
input C, D;
OFDX of1(Q, C, 1'b1, D) /* synthesis xc_props="FAST"*/;
endmodule
module OFD_FU (Q, C, D) /* synthesis xc_padmacro=1 */;
output Q /* synthesis .ispad=1 */;
input C, D;
OFDX of1(Q, C, 1'b1, D) /* synthesis xc_props="FAST, UNBONDED"*/;
endmodule
module OFD_S (Q, C, D) /* synthesis xc_padmacro=1 */;
output Q /* synthesis .ispad=1 */;
input C, D;
OFDX of1(Q, C, 1'b1, D) /* synthesis xc_props="SLOW"*/;
endmodule
module OFD_U (Q, C, D) /* synthesis xc_padmacro=1 */;
output Q /* synthesis .ispad=1 */;
input C, D;
OFDX of1(Q, C, 1'b1, D) /* synthesis xc_props="UNBONDED"*/;
endmodule
module OFD_MF (Q, C, D) /* synthesis xc_padmacro=1 */;
output Q /* synthesis .ispad=1 */;
input C, D;
OFDX of1(Q, C, 1'b1, D) /* synthesis xc_props="MEDFAST"*/;
endmodule
module OFD_MS (Q, C, D) /* synthesis xc_padmacro=1 */;
output Q /* synthesis .ispad=1 */;
input C, D;
OFDX of1(Q, C, 1'b1, D) /* synthesis xc_props="MEDSLOW"*/;
endmodule
module OFD_INT (Q, C, D) /* synthesis xc_padmacro=1 */;
output Q /* synthesis .ispad=1 */;
input C, D;
OFDX of1(Q, C, 1'b1, D);
endmodule
module OFDI (Q, C, D) /* synthesis xc_padmacro=1 */;
output Q /* synthesis .ispad=1 */;
input C, D;
OFDXI ofi1(Q, C, 1'b1, D);
endmodule
module OFDI_F (Q, C, D) /* synthesis xc_padmacro=1 */;
output Q /* synthesis .ispad=1 */;
input C, D;
OFDXI ofi1(Q, C, 1'b1, D) /* synthesis xc_props="FAST"*/;
endmodule
module OFDI_S (Q, C, D) /* synthesis xc_padmacro=1 */;
output Q /* synthesis .ispad=1 */;
input C, D;
OFDXI ofi1(Q, C, 1'b1, D) /* synthesis xc_props="SLOW"*/;
endmodule
module OFDI_MF (Q, C, D) /* synthesis xc_padmacro=1 */;
output Q /* synthesis .ispad=1 */;
input C, D;
OFDXI ofi1(Q, C, 1'b1, D) /* synthesis xc_props="MEDFAST"*/;
endmodule
module OFDI_MS (Q, C, D) /* synthesis xc_padmacro=1 */;
output Q /* synthesis .ispad=1 */;
input C, D;
OFDXI ofi1(Q, C, 1'b1, D) /* synthesis xc_props="MEDSLOW"*/;
endmodule
module OFDI_U (Q, C, D) /* synthesis xc_padmacro=1 */;
output Q /* synthesis .ispad=1 */;
input C, D;
OFDXI ofi1(Q, C, 1'b1, D) /* synthesis xc_props="UNBONDED"*/;
endmodule
module OFDI_INT (Q, C, D) /* synthesis xc_padmacro=1 */;
output Q /* synthesis .ispad=1 */;
input C, D;
OFDXI ofi1(Q, C, 1'b1, D);
endmodule
module OFDT (O, C, D, T) /* synthesis xc_padmacro=1 */;
output O /* synthesis .ispad=1 */;
input C, D, T;
OFDTX oft1(O, C, 1'b1, D, T);
endmodule
module OFDT_F (O, C, D, T) /* synthesis xc_padmacro=1 */;
output O /* synthesis .ispad=1 */;
input C, D, T;
OFDTX oft1(O, C, 1'b1, D, T) /* synthesis xc_props="FAST"*/;
endmodule
module OFDT_S (O, C, D, T) /* synthesis xc_padmacro=1 */;
output O /* synthesis .ispad=1 */;
input C, D, T;
OFDTX oft1(O, C, 1'b1, D, T) /* synthesis xc_props="SLOW"*/;
endmodule
module OFDT_MF (O, C, D, T) /* synthesis xc_padmacro=1 */;
output O /* synthesis .ispad=1 */;
input C, D, T;
OFDTX oft1(O, C, 1'b1, D, T) /* synthesis xc_props="MEDFAST"*/;
endmodule
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