📄 xc4000.v

📁 Xilinx Ise 官方源代码盘第四章
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module AND2 (O, I0, I1) /* synthesis syn_black_box xc_alias="AND"*/;
    output   O;
    input    I0, I1;
endmodule
module AND3 (O, I0, I1, I2) /* synthesis syn_black_box xc_alias="AND"*/;
    output   O;
    input    I0, I1, I2;
endmodule
module AND4 (O, I0, I1, I2, I3) /* synthesis syn_black_box xc_alias="AND"*/;
    output   O;
    input    I0, I1, I2, I3;
endmodule
module AND5 (O, I0, I1, I2, I3, I4) /* synthesis syn_black_box xc_alias="AND" */;
    output   O;
    input    I0, I1, I2, I3, I4;
endmodule
module TDI(I)/*synthesis syn_black_box*/;
output I /*synthesis .ispad=1*/;
endmodule

module TCK(I)/*synthesis syn_black_box*/;
output I /*synthesis .ispad=1*/;
endmodule

module TMS(I)/*synthesis syn_black_box*/;
output I /*synthesis .ispad=1*/;
endmodule

module TDO(O) /*synthesis syn_black_box .noprune=1 */;
input  O /*synthesis .ispad=1*/;
endmodule

//
// Note: Port directions are compatable with an M1.5 patch
// available from Xilinx.
//
module MD0(I)/* synthesis syn_black_box .noprune=1 */;
output I /* synthesis .ispad=1  */;
endmodule

module MD2(I)/* synthesis syn_black_box .noprune=1 */;
output I /* synthesis .ispad=1  */;
endmodule

module MD1(O)/* synthesis syn_black_box .noprune=1 */;
input O /* synthesis  .ispad=1 */;
endmodule

module BSCAN(DRCK, IDLE, SEL1, SEL2, TDO, TCK, TDI, TDO1, TDO2, TMS) /* synthesis syn_black_box */;
  output  DRCK, IDLE, SEL1, SEL2, TDO;
  input TCK, TDI, TDO1, TDO2, TMS;
endmodule
module BUFF (O, I) /* synthesis syn_black_box xc_alias="BUF"*/;
    output   O;
    input    I;
endmodule
/* for 4000X family only */
module BUFGE(O, I) /* synthesis syn_black_box */;
    output O;
    input I;
endmodule
module BUFGLS (O, I) /* synthesis syn_black_box */;
    output   O;
    input    I ;
endmodule
module BUFG (O, I) /* synthesis syn_black_box */;
    output   O;
    input    I ;
endmodule
module BUFG_F (O, I);
    output   O;
    input    I ;

	BUFG b(O,I) /* synthesis xc_props = "FAST" */;
endmodule
module BUFGP (O, I) /* synthesis syn_black_box */;
    output   O;
    input    I ;
endmodule
module BUFGP_F (O, I);
    output   O;
    input    I ;
	BUFGP b(O,I) /* synthesis xc_props = "FAST" */;
endmodule
module BUFGS (O, I) /* synthesis syn_black_box */;
    output   O;
    input    I ;
endmodule
module BUFGS_F (O, I);
    output   O;
    input    I; 
	BUFGS b(O, I) /* synthesis xc_props = "FAST" */;
endmodule
module BUFT (O, I, T) /* synthesis syn_black_box xc_alias="TBUF"*/;
    output   O /* synthesis syn_tristate=1 */;
    input    I, T;
assign O = ~T ? I : 'bz;
endmodule
module CY4 (COUT, COUT0, A0, A1, ADD, B0, B1, C0, C1, C2, C3, C4, C5, C6, C7, CIN ) /* synthesis syn_black_box */;
    output   COUT, COUT0;
    input    A0, A1, ADD, B0, B1, C0, C1, C2, C3, C4, C5, C6, C7, CIN;
    // default unconnected input pins to 0
endmodule
module CY4_01 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_02 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_03 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_04 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_05 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_06 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_07 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_08 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_09 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_10 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_11 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_12 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_13 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_14 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_15 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_16 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_17 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_18 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_19 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_20 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_21 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_22 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_23 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_24 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_25 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_26 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_27 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_28 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_29 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_30 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_31 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_32 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_33 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_34 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_35 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_36 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_37 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_38 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_39 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_40 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_41 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module CY4_42 (C0, C1, C2, C3, C4, C5, C6, C7) /* synthesis syn_black_box .noprune=1 */;
    output   C0, C1, C2, C3, C4, C5, C6, C7;
endmodule
module FDCE (Q, C, CE, CLR, D) /* synthesis syn_black_box */;
    output   Q;
    input    C, CE, CLR, D;
endmodule
module FDC (Q, C, CLR, D);
    output   Q;
    input    C, CLR, D;
	FDCE f1(Q, C, 1'b1, CLR, D);
endmodule
module FDCE_INT (Q, C, CE, CLR, D);
    output   Q;
    input    C, CE, CLR, D;
	FDCE f1(Q, C, CE, CLR, D);
endmodule
module FDPE (Q, C, CE, D, PRE) /* synthesis syn_black_box */;
    output   Q;
    input    C, CE, D, PRE;
endmodule
module FDP (Q, C, D, PRE);
    output   Q;
    input    C, D, PRE;
	FDPE f1(Q, C, 1'b1, D, PRE);
endmodule
module FDPE_INT (Q, C, CE, D, PRE);
    output   Q;
    input    C, CE, D, PRE;
	FDPE f1(Q, C, CE, D, PRE);
endmodule
module FMAP (I1, I2, I3, I4, O) /* synthesis syn_black_box */;
    input    I1, I2, I3, I4;
    output   O;
endmodule
module FMAP_PUC (I1, I2, I3, I4, O) /* synthesis syn_black_box xc_alias="FMAP" xc_props="MAP=PUC"*/;
    input    I1, I2, I3, I4;
    output   O;
endmodule
module FMAP_PLC (I1, I2, I3, I4, O) /* synthesis syn_black_box xc_alias="FMAP" xc_props="MAP=PLC"*/;
    input    I1, I2, I3, I4;
    output   O;
endmodule
module FMAP_PUO (I1, I2, I3, I4, O) /* synthesis syn_black_box xc_alias="FMAP" xc_props="MAP=PUO"*/;
    input    I1, I2, I3, I4;
    output   O;
endmodule
module FMAP_PLO (I1, I2, I3, I4, O) /* synthesis syn_black_box xc_alias="FMAP" xc_props="MAP=PLO"*/;
    input    I1, I2, I3, I4;
    output   O;
endmodule
module HMAP (I1, I2, I3, O) /* synthesis syn_black_box */;
    input    I1, I2, I3;
    output  O;
endmodule
module HMAP_PUC (I1, I2, I3, O) /* synthesis syn_black_box xc_alias="HMAP" xc_props="MAP=PUC"*/;
    input    I1, I2, I3;
    output  O;
endmodule
module IBUF (O, I) /* synthesis syn_black_box */; 
	output   O;
 	input    I /* synthesis .ispad=1 */;
endmodule
module IBUF_U (O, I) /* synthesis syn_black_box xc_alias="IBUF" xc_props="UNBONDED"*/; 
	output   O;
 	input    I /* synthesis .ispad=1 */;
endmodule
module IBUF_CMOS (O, I) /* synthesis syn_black_box xc_alias="IBUF" xc_props="CMOS"*/; 
	output   O;
 	input    I /* synthesis .ispad=1 */;
endmodule
module IBUF_TTL (O, I) /* synthesis syn_black_box xc_alias="IBUF" xc_props="TTL"*/; 
	output   O;
 	input    I /* synthesis .ispad=1 */;
endmodule
module IFD (Q, C, D)	/* synthesis xc_padmacro=1 */;
    output   Q;
    input    C;
    input    D /* synthesis .ispad=1 */;
	IFDX if1(Q, C, 1'b1, D);
endmodule
module IFD_F (Q, C, D)	/* synthesis xc_padmacro=1 */;
    output   Q;
    input    C;
    input    D /* synthesis .ispad=1 */;
	IFDX if1(Q, C, 1'b1, D) /* synthesis xc_props = "NODELAY" */;
endmodule
module IFD_U (Q, C, D) /* synthesis xc_padmacro=1 xc_props="UNBONDED" */;
    output   Q;
    input    C;
    input    D /* synthesis .ispad=1 */;
	IFDX if1(Q, C, 1'b1, D);
endmodule
module IFD_INT (Q, C, D)	/* synthesis xc_padmacro=1 */;
    output   Q;
    input    C;
    input D /* synthesis .ispad=1 */;
	IFDX if1(Q, C, 1'b1, D);
endmodule
module IFDI (Q, C, D)	/* synthesis xc_padmacro=1 */;
    output   Q;
    input    C;
    input D /* synthesis .ispad=1 */;
	IFDXI ifi1(Q, C, 1'b1, D);
endmodule
module IFDI_F (Q, C, D)	/* synthesis xc_padmacro=1 */;
    output   Q;
    input    C;
    input D /* synthesis .ispad=1 */;
	IFDXI ifi1(Q, C, 1'b1, D) /* synthesis xc_props="NODELAY"*/;
endmodule
module IFDI_U (Q, C, D) /* synthesis xc_padmacro=1 xc_props="UNBONDED"*/;
    output   Q;
    input    C;
    input D /* synthesis .ispad=1 */;
	IFDXI ifi1(Q, C, 1'b1, D);
endmodule
module IFDI_INT (Q, C, D)	/* synthesis xc_padmacro=1 */;
    output   Q;
    input    C;
    input   D /* synthesis .ispad=1 */;
	IFDXI ifi1(Q, C, 1'b1, D);
endmodule
module IFDX (Q, C, CE, D) /* synthesis syn_black_box */;
    output Q;
	input C;
	input CE;
	input D /* synthesis .ispad= 1 */;
endmodule
module IFDXI (Q, C, CE, D) /* synthesis syn_black_box */;
    output Q;
	input C;
	input CE;
	input D /* synthesis .ispad= 1 */;
endmodule
module ILD_1 (Q, D, G) 	/* synthesis xc_padmacro=1 */;
    output   Q;
    input    G;
    input    D /* synthesis .ispad=1 */;
	ILDX_1 il1(Q, D, G, 1'b1);
endmodule
module ILD_1F (Q, D, G) /* synthesis xc_padmacro=1 xc_props="NODELAY"*/;
    output   Q;
    input    G;
    input    D /* synthesis .ispad=1 */;
	ILDX_1 il1(Q, D, G, 1'b1);
endmodule
module ILD_1U (Q, D, G) /* synthesis xc_padmacro=1 xc_props="UNBONDED"*/;
    output   Q;
    input    G;
    input    D /* synthesis .ispad=1 */;
	ILDX_1 il1(Q, D, G, 1'b1);
endmodule
module ILD_1_INT (Q, D, G)	/* synthesis xc_padmacro=1 */;
    output   Q;
    input    G;
    input    D /* synthesis .ispad=1 */;
	ILDX_1 il1(Q, D, G, 1'b1);
endmodule
module ILDI_1 (Q, D, G) 	/* synthesis xc_padmacro=1 */;
    output   Q;
    input    G;
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