unisim.vhd

Xilinx Ise 官方源代码盘 第四章

   R : in std_logic
 );
end component;
attribute syn_black_box of FDRE : component is true;
component FDRE_1
 port (
   Q : out std_logic;
   C : in std_logic;
   CE : in std_logic;
   D : in std_logic;
   R : in std_logic
 );
end component;
attribute syn_black_box of FDRE_1 : component is true;
component FDRS
 port (
   Q : out std_logic;
   C : in std_logic;
   D : in std_logic;
   R : in std_logic;
   S : in std_logic
 );
end component;
attribute syn_black_box of FDRS : component is true;
component FDRSE
 port (
   Q : out std_logic;
   C : in std_logic;
   CE : in std_logic;
   D : in std_logic;
   R : in std_logic;
   S : in std_logic
 );
end component;
attribute syn_black_box of FDRSE : component is true;
component FDRSE_1
 port (
   Q : out std_logic;
   C : in std_logic;
   CE : in std_logic;
   D : in std_logic;
   R : in std_logic;
   S : in std_logic
 );
end component;
attribute syn_black_box of FDRSE_1 : component is true;
component FDRS_1
 port (
   Q : out std_logic;
   C : in std_logic;
   D : in std_logic;
   R : in std_logic;
   S : in std_logic
 );
end component;
attribute syn_black_box of FDRS_1 : component is true;
component FDR_1
 port (
   Q : out std_logic;
   C : in std_logic;
   D : in std_logic;
   R : in std_logic
 );
end component;
attribute syn_black_box of FDR_1 : component is true;
component FDS
 port (
   Q : out std_logic;
   C : in std_logic;
   D : in std_logic;
   S : in std_logic
 );
end component;
attribute syn_black_box of FDS : component is true;
component FDSE
 port (
   Q : out std_logic;
   C : in std_logic;
   CE : in std_logic;
   D : in std_logic;
   S : in std_logic
 );
end component;
attribute syn_black_box of FDSE : component is true;
component FDSE_1
 port (
   Q : out std_logic;
   C : in std_logic;
   CE : in std_logic;
   D : in std_logic;
   S : in std_logic
 );
end component;
attribute syn_black_box of FDSE_1 : component is true;
component FDS_1
 port (
   Q : out std_logic;
   C : in std_logic;
   D : in std_logic;
   S : in std_logic
 );
end component;
attribute syn_black_box of FDS_1 : component is true;
component FD_1
 port (
   Q : out std_logic;
   C : in std_logic;
   D : in std_logic
 );
end component;
attribute syn_black_box of FD_1 : component is true;
component GND
 port (
   G : out std_logic
 );
end component;
attribute syn_black_box of GND : component is true;
attribute syn_noprune of GND : component is true;
component IBUF
 generic (
   IOSTANDARD : string := "default"
 );
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF : component is true;
component IBUFDS
 generic (
   IOSTANDARD : string := "default"
 );
 port (
   O : out std_logic;
   I : in std_logic;
   IB : in std_logic
 );
end component;
attribute syn_black_box of IBUFDS : component is true;
component IBUFDS_BLVDS_25
 port (
   O : out std_logic;
   I : in std_logic;
   IB : in std_logic
 );
end component;
attribute syn_black_box of IBUFDS_BLVDS_25 : component is true;
component IBUFDS_LDT_25
 port (
   O : out std_logic;
   I : in std_logic;
   IB : in std_logic
 );
end component;
attribute syn_black_box of IBUFDS_LDT_25 : component is true;
component IBUFDS_LVDSEXT_25
 port (
   O : out std_logic;
   I : in std_logic;
   IB : in std_logic
 );
end component;
attribute syn_black_box of IBUFDS_LVDSEXT_25 : component is true;
component IBUFDS_LVDSEXT_33
 port (
   O : out std_logic;
   I : in std_logic;
   IB : in std_logic
 );
end component;
attribute syn_black_box of IBUFDS_LVDSEXT_33 : component is true;
component IBUFDS_LVDS_25
 port (
   O : out std_logic;
   I : in std_logic;
   IB : in std_logic
 );
end component;
attribute syn_black_box of IBUFDS_LVDS_25 : component is true;
component IBUFDS_LVDS_33
 port (
   O : out std_logic;
   I : in std_logic;
   IB : in std_logic
 );
end component;
attribute syn_black_box of IBUFDS_LVDS_33 : component is true;
component IBUFDS_LVPECL_33
 port (
   O : out std_logic;
   I : in std_logic;
   IB : in std_logic
 );
end component;
attribute syn_black_box of IBUFDS_LVPECL_33 : component is true;
component IBUFDS_ULVDS_25
 port (
   O : out std_logic;
   I : in std_logic;
   IB : in std_logic
 );
end component;
attribute syn_black_box of IBUFDS_ULVDS_25 : component is true;
component IBUFG
 generic (
   IOSTANDARD : string := "default"
 );
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG : component is true;
component IBUFGDS
 generic (
   IOSTANDARD : string := "default"
 );
 port (
   O : out std_logic;
   I : in std_logic;
   IB : in std_logic
 );
end component;
attribute syn_black_box of IBUFGDS : component is true;
component IBUFGDS_BLVDS_25
 port (
   O : out std_logic;
   I : in std_logic;
   IB : in std_logic
 );
end component;
attribute syn_black_box of IBUFGDS_BLVDS_25 : component is true;
component IBUFGDS_LDT_25
 port (
   O : out std_logic;
   I : in std_logic;
   IB : in std_logic
 );
end component;
attribute syn_black_box of IBUFGDS_LDT_25 : component is true;
component IBUFGDS_LVDSEXT_25
 port (
   O : out std_logic;
   I : in std_logic;
   IB : in std_logic
 );
end component;
attribute syn_black_box of IBUFGDS_LVDSEXT_25 : component is true;
component IBUFGDS_LVDSEXT_33
 port (
   O : out std_logic;
   I : in std_logic;
   IB : in std_logic
 );
end component;
attribute syn_black_box of IBUFGDS_LVDSEXT_33 : component is true;
component IBUFGDS_LVDS_25
 port (
   O : out std_logic;
   I : in std_logic;
   IB : in std_logic
 );
end component;
attribute syn_black_box of IBUFGDS_LVDS_25 : component is true;
component IBUFGDS_LVDS_33
 port (
   O : out std_logic;
   I : in std_logic;
   IB : in std_logic
 );
end component;
attribute syn_black_box of IBUFGDS_LVDS_33 : component is true;
component IBUFGDS_LVPECL_33
 port (
   O : out std_logic;
   I : in std_logic;
   IB : in std_logic
 );
end component;
attribute syn_black_box of IBUFGDS_LVPECL_33 : component is true;
component IBUFGDS_ULVDS_25
 port (
   O : out std_logic;
   I : in std_logic;
   IB : in std_logic
 );
end component;
attribute syn_black_box of IBUFGDS_ULVDS_25 : component is true;
component IBUFG_AGP
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_AGP : component is true;
component IBUFG_CTT
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_CTT : component is true;
component IBUFG_GTL
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_GTL : component is true;
component IBUFG_GTL_DCI
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_GTL_DCI : component is true;
component IBUFG_GTLP
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_GTLP : component is true;
component IBUFG_GTLP_DCI
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_GTLP_DCI : component is true;
component IBUFG_HSTL_I
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_HSTL_I : component is true;
component IBUFG_HSTL_I_18
  port (
    O : out std_logic;
    I : in std_logic
  );
end component;
attribute syn_black_box of IBUFG_HSTL_I_18 : component is true;
component IBUFG_HSTL_I_DCI
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_HSTL_I_DCI : component is true;
component IBUFG_HSTL_I_DCI_18
  port (
    O : out std_logic;
    I : in std_logic
  );
end component;
attribute syn_black_box of IBUFG_HSTL_I_DCI_18 : component is true;
component IBUFG_HSTL_II
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_HSTL_II : component is true;
component IBUFG_HSTL_II_18
  port (
    O : out std_logic;
    I : in std_logic
  );
end component;
attribute syn_black_box of IBUFG_HSTL_II_18 : component is true;
component IBUFG_HSTL_II_DCI
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_HSTL_II_DCI : component is true;
component IBUFG_HSTL_II_DCI_18
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_HSTL_II_DCI_18 : component is true;
component IBUFG_HSTL_III
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_HSTL_III : component is true;
component IBUFG_HSTL_III_18
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_HSTL_III_18 : component is true;
component IBUFG_HSTL_III_DCI
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_HSTL_III_DCI : component is true;
component IBUFG_HSTL_III_DCI_18
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_HSTL_III_DCI_18 : component is true;
component IBUFG_HSTL_IV
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_HSTL_IV : component is true;
component IBUFG_HSTL_IV_18
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_HSTL_IV_18 : component is true;
component IBUFG_HSTL_IV_DCI
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_HSTL_IV_DCI : component is true;
component IBUFG_HSTL_IV_DCI_18
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_HSTL_IV_DCI_18 : component is true;
component IBUFG_LVDCI_15
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_LVDCI_15 : component is true;
component IBUFG_LVDCI_18
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_LVDCI_18 : component is true;
component IBUFG_LVDCI_25
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_LVDCI_25 : component is true;
component IBUFG_LVDCI_33
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_LVDCI_33 : component is true;
component IBUFG_LVDCI_DV2_15
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_LVDCI_DV2_15 : component is true;
component IBUFG_LVDCI_DV2_18
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_LVDCI_DV2_18 : component is true;
component IBUFG_LVDCI_DV2_25
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_LVDCI_DV2_25 : component is true;
component IBUFG_LVDCI_DV2_33
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_LVDCI_DV2_33 : component is true;
component IBUFG_LVTTL
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_LVTTL : component is true;
component IBUFG_LVCMOS15
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_LVCMOS15 : component is true;
component IBUFG_LVCMOS18
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_LVCMOS18 : component is true;
component IBUFG_LVCMOS2
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_LVCMOS2 : component is true;
component IBUFG_LVCMOS25
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_LVCMOS25 : component is true;
component IBUFG_LVCMOS33
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_LVCMOS33 : component is true;
component IBUFG_LVDS
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_LVDS : component is true;
component IBUFG_LVPECL
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_LVPECL : component is true;
component IBUFG_PCI33_3
 port (
   O : out std_logic;