xc9500.vhd

Xilinx Ise 官方源代码盘 第四章

end component;
attribute syn_black_box of NOR2 : component is true;
component NOR2B1
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic
 );
end component;
attribute syn_black_box of NOR2B1 : component is true;
component NOR2B2
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic
 );
end component;
attribute syn_black_box of NOR2B2 : component is true;
component NOR3
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic
 );
end component;
attribute syn_black_box of NOR3 : component is true;
component NOR3B1
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic
 );
end component;
attribute syn_black_box of NOR3B1 : component is true;
component NOR3B2
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic
 );
end component;
attribute syn_black_box of NOR3B2 : component is true;
component NOR3B3
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic
 );
end component;
attribute syn_black_box of NOR3B3 : component is true;
component NOR4
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of NOR4 : component is true;
component NOR4B1
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of NOR4B1 : component is true;
component NOR4B2
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of NOR4B2 : component is true;
component NOR4B3
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of NOR4B3 : component is true;
component NOR4B4
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of NOR4B4 : component is true;
component NOR5
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of NOR5 : component is true;
component NOR5B1
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of NOR5B1 : component is true;
component NOR5B2
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of NOR5B2 : component is true;
component NOR5B3
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of NOR5B3 : component is true;
component NOR5B4
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of NOR5B4 : component is true;
component NOR5B5
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of NOR5B5 : component is true;
component NOR6
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic;
   I5 : in std_logic
 );
end component;
attribute syn_black_box of NOR6 : component is true;
component NOR7
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic;
   I5 : in std_logic;
   I6 : in std_logic
 );
end component;
attribute syn_black_box of NOR7 : component is true;
component NOR8
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic;
   I5 : in std_logic;
   I6 : in std_logic;
   I7 : in std_logic
 );
end component;
attribute syn_black_box of NOR8 : component is true;
component NOR9
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic;
   I5 : in std_logic;
   I6 : in std_logic;
   I7 : in std_logic;
   I8 : in std_logic
 );
end component;
attribute syn_black_box of NOR9 : component is true;
component OBUF
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of OBUF : component is true;
attribute black_box_pad_pin of OBUF : component is "O";
component OBUFE
 port (
   O : out std_logic;
   E : in std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of OBUFE : component is true;
attribute black_box_pad_pin of OBUFE : component is "O";
attribute black_box_tri_pins of OBUFE : component is "O";
component OBUFT
 port (
   O : out std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of OBUFT : component is true;
attribute black_box_pad_pin of OBUFT : component is "O";
attribute black_box_tri_pins of OBUFT : component is "O";
component OR2
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic
 );
end component;
attribute syn_black_box of OR2 : component is true;
component OR2B1
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic
 );
end component;
attribute syn_black_box of OR2B1 : component is true;
component OR2B2
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic
 );
end component;
attribute syn_black_box of OR2B2 : component is true;
component OR3
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic
 );
end component;
attribute syn_black_box of OR3 : component is true;
component OR3B1
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic
 );
end component;
attribute syn_black_box of OR3B1 : component is true;
component OR3B2
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic
 );
end component;
attribute syn_black_box of OR3B2 : component is true;
component OR3B3
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic
 );
end component;
attribute syn_black_box of OR3B3 : component is true;
component OR4
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of OR4 : component is true;
component OR4B1
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of OR4B1 : component is true;
component OR4B2
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of OR4B2 : component is true;
component OR4B3
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of OR4B3 : component is true;
component OR4B4
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of OR4B4 : component is true;
component OR5
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of OR5 : component is true;
component OR5B1
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of OR5B1 : component is true;
component OR5B2
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of OR5B2 : component is true;
component OR5B3
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of OR5B3 : component is true;
component OR5B4
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of OR5B4 : component is true;
component OR5B5
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of OR5B5 : component is true;
component OR6
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic;
   I5 : in std_logic
 );
end component;
attribute syn_black_box of OR6 : component is true;
component OR7
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic;
   I5 : in std_logic;
   I6 : in std_logic
 );
end component;
attribute syn_black_box of OR7 : component is true;
component OR8
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic;
   I5 : in std_logic;
   I6 : in std_logic;
   I7 : in std_logic
 );
end component;
attribute syn_black_box of OR8 : component is true;
component OR9
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic;
   I5 : in std_logic;
   I6 : in std_logic;
   I7 : in std_logic;
   I8 : in std_logic
 );
end component;
attribute syn_black_box of OR9 : component is true;
component VCC
 port (
   P : out std_logic
 );
end component;
attribute syn_black_box of VCC : component is true;
attribute syn_noprune of VCC : component is true;
component XNOR2
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic
 );
end component;
attribute syn_black_box of XNOR2 : component is true;
component XNOR3
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic
 );
end component;
attribute syn_black_box of XNOR3 : component is true;
component XNOR4
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of XNOR4 : component is true;
component XOR2
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic
 );
end component;
attribute syn_black_box of XOR2 : component is true;
component XOR3
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic
 );
end component;
attribute syn_black_box of XOR3 : component is true;
component XOR4
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of XOR4 : component is true;
component XOR5
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of XOR5 : component is true;
component XOR6
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic;
   I5 : in std_logic
 );
end component;
attribute syn_black_box of XOR6 : component is true;
component XOR7
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic;
   I5 : in std_logic;
   I6 : in std_logic
 );
end component;
attribute syn_black_box of XOR7 : component is true;
component XOR8
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic;
   I5 : in std_logic;
   I6 : in std_logic;
   I7 : in std_logic
 );
end component;
attribute syn_black_box of XOR8 : component is true;
end package components;