xc9500.v

Xilinx Ise 官方源代码盘 第四章

module AND2(O, I0, I1) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
endmodule
module AND2B1(O, I0, I1) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
endmodule
module AND2B2(O, I0, I1) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
endmodule
module AND3(O, I0, I1, I2) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
endmodule
module AND3B1(O, I0, I1, I2) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
endmodule
module AND3B2(O, I0, I1, I2) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
endmodule
module AND3B3(O, I0, I1, I2) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
endmodule
module AND4(O, I0, I1, I2, I3) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
module AND4B1(O, I0, I1, I2, I3) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
module AND4B2(O, I0, I1, I2, I3) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
module AND4B3(O, I0, I1, I2, I3) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
module AND4B4(O, I0, I1, I2, I3) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
module AND5(O, I0, I1, I2, I3, I4) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
module AND5B1(O, I0, I1, I2, I3, I4) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
module AND5B2(O, I0, I1, I2, I3, I4) /* synthesis syn_black_box  */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
module AND5B3(O, I0, I1, I2, I3, I4) /* synthesis syn_black_box  */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
module AND5B4(O, I0, I1, I2, I3, I4) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
module AND5B5(O, I0, I1, I2, I3, I4) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
module AND6(O, I0, I1, I2, I3, I4, I5) /* synthesis syn_black_box  */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
input I5;
endmodule
module AND7(O, I0, I1, I2, I3, I4, I5, I6) /* synthesis syn_black_box  */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
input I5;
input I6;
endmodule
module AND8(O, I0, I1, I2, I3, I4, I5, I6, I7) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
input I5;
input I6;
input I7;
endmodule
module AND9(O, I0, I1, I2, I3, I4, I5, I6, I7, I8) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
input I5;
input I6;
input I7;
input I8;
endmodule
module BUF(O, I) /* synthesis syn_black_box */;
output O;
input I;
endmodule
//BUFE is not supported for XC9500XL and XC9500XV devices
module BUFE(O, I, E) /* synthesis syn_black_box */;
output O /* synthesis syn_tristate=1 */;
input I;
input E;
endmodule
module BUFG(O, I) /* synthesis syn_black_box */;
output O;
input I /* synthesis .ispad = 1 */;
endmodule
module BUFGSR(O, I) /* synthesis syn_black_box */;
output O;
input I /* synthesis .ispad = 1 */;
endmodule
module BUFGTS(O, I) /* synthesis syn_black_box */;
output O;
input I /* syntesis .ispad = 1 */;
endmodule
//BUFT is not supported for XC9500XL and XC9500XV devices
module BUFT(O, I, T) /* synthesis syn_black_box */;
output O /* synthesis syn_tristate=1 */;
input I;
input T;
endmodule
module FDCE(Q, C, CE, CLR, D) /* synthesis syn_black_box */;
output Q;
input C;
input CE;
input CLR;
input D;
endmodule
module FDCP(Q, C, CLR, D, PRE) /* synthesis syn_black_box */;
output Q;
input C;
input CLR;
input D;
input PRE;
endmodule
module FDPE(Q, C, CE, D, PRE) /* synthesis syn_black_box */;
output Q;
input C;
input CE;
input D;
input PRE;
endmodule
module FTCP(Q, C, CLR, PRE, T) /* synthesis syn_black_box */;
output Q;
input C;
input CLR;
input PRE;
input T;
endmodule
module GND(G) /* synthesis syn_black_box syn_noprune=1 */;
output G;
endmodule
module IBUF(O, I) /* synthesis syn_black_box */;
output O;
input I /* synthesis .ispad=1 */;
endmodule
module INV(O, I) /* synthesis syn_black_box */;
output O;
input I;
endmodule
module NAND2(O, I0, I1) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
endmodule
module NAND2B1(O, I0, I1) /* synthesis syn_black_box  */;
output O;
input I0;
input I1;
endmodule
module NAND2B2(O, I0, I1) /* synthesis syn_black_box  */;
output O;
input I0;
input I1;
endmodule
module NAND3(O, I0, I1, I2) /* synthesis syn_black_box  */;
output O;
input I0;
input I1;
input I2;
endmodule
module NAND3B1(O, I0, I1, I2) /* synthesis syn_black_box  */;
output O;
input I0;
input I1;
input I2;
endmodule
module NAND3B2(O, I0, I1, I2) /* synthesis syn_black_box  */;
output O;
input I0;
input I1;
input I2;
endmodule
module NAND3B3(O, I0, I1, I2) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
endmodule
module NAND4(O, I0, I1, I2, I3) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
module NAND4B1(O, I0, I1, I2, I3) /* synthesis syn_black_box  */;
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
module NAND4B2(O, I0, I1, I2, I3) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
module NAND4B3(O, I0, I1, I2, I3) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
module NAND4B4(O, I0, I1, I2, I3) /* synthesis syn_black_box  */;
output O;
input I0;
input I1;
input I2;
input I3;
endmodule
module NAND5(O, I0, I1, I2, I3, I4) /* synthesis syn_black_box  */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
module NAND5B1(O, I0, I1, I2, I3, I4) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
module NAND5B2(O, I0, I1, I2, I3, I4) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
module NAND5B3(O, I0, I1, I2, I3, I4) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
module NAND5B4(O, I0, I1, I2, I3, I4) /* synthesis syn_black_box  */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
module NAND5B5(O, I0, I1, I2, I3, I4) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
endmodule
module NAND6(O, I0, I1, I2, I3, I4, I5) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
input I5;
endmodule
module NAND7(O, I0, I1, I2, I3, I4, I5, I6) /* synthesis syn_black_box  */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
input I5;
input I6;
endmodule
module NAND8(O, I0, I1, I2, I3, I4, I5, I6, I7) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
input I5;
input I6;
input I7;
endmodule
module NAND9(O, I0, I1, I2, I3, I4, I5, I6, I7, I8) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
input I2;
input I3;
input I4;
input I5;
input I6;
input I7;
input I8;
endmodule
module NOR2(O, I0, I1) /* synthesis syn_black_box  */;
output O;
input I0;
input I1;
endmodule
module NOR2B1(O, I0, I1) /* synthesis syn_black_box */;
output O;
input I0;
input I1;
endmodule
module NOR2B2(O, I0, I1) /* synthesis syn_black_box  */;
output O;
input I0;