virtexe.v

Xilinx Ise 官方源代码盘 第四章

output O;
input I;
endmodule
module OBUF_HSTL_I(O, I); // synthesis syn_black_box
output O;
input I;
endmodule
module OBUF_HSTL_III(O, I); // synthesis syn_black_box
output O;
input I;
endmodule
module OBUF_HSTL_IV(O, I); // synthesis syn_black_box
output O;
input I;
endmodule
module OBUF_LVCMOS18(O, I); // synthesis syn_black_box
output O;
input I;
endmodule
module OBUF_LVCMOS2(O, I); // synthesis syn_black_box
output O;
input I;
endmodule
module OBUF_LVDS(O, I); // synthesis syn_black_box
output O;
input I;
endmodule
module OBUF_LVPECL(O, I); // synthesis syn_black_box
output O;
input I;
endmodule
module OBUF_PCI33_3(O, I); // synthesis syn_black_box
output O;
input I;
endmodule
module OBUF_PCI66_3(O, I); // synthesis syn_black_box
output O;
input I;
endmodule
module OBUF_SSTL2_I(O, I); // synthesis syn_black_box
output O;
input I;
endmodule
module OBUF_SSTL2_II(O, I); // synthesis syn_black_box
output O;
input I;
endmodule
module OBUF_SSTL3_I(O, I); // synthesis syn_black_box
output O;
input I;
endmodule
module OBUF_SSTL3_II(O, I); // synthesis syn_black_box
output O;
input I;
endmodule
module OBUF_S_12(O, I); // synthesis syn_black_box
output O;
input I;
endmodule
module OBUF_S_16(O, I); // synthesis syn_black_box
output O;
input I;
endmodule
module OBUF_S_2(O, I); // synthesis syn_black_box
output O;
input I;
endmodule
module OBUF_S_24(O, I); // synthesis syn_black_box
output O;
input I;
endmodule
module OBUF_S_4(O, I); // synthesis syn_black_box
output O;
input I;
endmodule
module OBUF_S_6(O, I); // synthesis syn_black_box
output O;
input I;
endmodule
module OBUF_S_8(O, I); // synthesis syn_black_box
output O;
input I;
endmodule
module PULLDOWN(O); /* synthesis syn_black_box .noprune=1 */
output O /* synthesis syn_not_a_driver=1 */;
endmodule
module PULLUP(O); /* synthesis syn_black_box .noprune=1 */
output O /* synthesis syn_not_a_driver=1 */;
endmodule
module RAM16X1D(DPO, SPO, A0, A1, A2, A3, D, DPRA0, DPRA1, DPRA2, DPRA3, WCLK, WE); // synthesis syn_black_box
parameter INIT = 16'h0000;
output DPO;
output SPO;
input A0;
input A1;
input A2;
input A3;
input D;
input DPRA0;
input DPRA1;
input DPRA2;
input DPRA3;
input WCLK;
input WE;
endmodule
module RAM16X1D_1(DPO, SPO, A0, A1, A2, A3, D, DPRA0, DPRA1, DPRA2, DPRA3, WCLK, WE); // synthesis syn_black_box
parameter INIT = 16'h0000;
output DPO;
output SPO;
input A0;
input A1;
input A2;
input A3;
input D;
input DPRA0;
input DPRA1;
input DPRA2;
input DPRA3;
input WCLK;
input WE;
endmodule
module RAM16X1S(O, A0, A1, A2, A3, D, WCLK, WE); // synthesis syn_black_box
parameter INIT = 16'h0000;
output O;
input A0;
input A1;
input A2;
input A3;
input D;
input WCLK;
input WE;
endmodule
module RAM16X1S_1(O, A0, A1, A2, A3, D, WCLK, WE); // synthesis syn_black_box
parameter INIT = 16'h0000;
output O;
input A0;
input A1;
input A2;
input A3;
input D;
input WCLK;
input WE;
endmodule
module RAM32X1S(O, A0, A1, A2, A3, A4, D, WCLK, WE); // synthesis syn_black_box
parameter INIT = 32'h00000000;
output O;
input A0;
input A1;
input A2;
input A3;
input A4;
input D;
input WCLK;
input WE;
endmodule
module RAM32X1S_1(O, A0, A1, A2, A3, A4, D, WCLK, WE); // synthesis syn_black_box
parameter INIT = 32'h00000000;
output O;
input A0;
input A1;
input A2;
input A3;
input A4;
input D;
input WCLK;
input WE;
endmodule
module ROM16X1(O, A0, A1, A2, A3); // synthesis syn_black_box
parameter INIT = 16'h0000;
output O;
input A0;
input A1;
input A2;
input A3;
endmodule
module ROM32X1(O, A0, A1, A2, A3, A4); // synthesis syn_black_box
parameter INIT = 32'h00000000;
output O;
input A0;
input A1;
input A2;
input A3;
input A4;
endmodule
module RAMB4_S1(DO, ADDR, DI, EN, CLK, WE, RST); // synthesis syn_black_box
output [0:0] DO;
input [11:0] ADDR;
input [0:0] DI;
input EN;
input CLK;
input WE;
input RST;
endmodule
module RAMB4_S16(DO, ADDR, DI, EN, CLK, WE, RST); // synthesis syn_black_box
output [15:0] DO;
input [7:0] ADDR;
input [15:0] DI;
input EN;
input CLK;
input WE;
input RST;
endmodule
module RAMB4_S16_S16(DOA, DOB, ADDRA, DIA, ENA, CLKA, WEA, RSTA, ADDRB, DIB, ENB, CLKB, WEB, RSTB); // synthesis syn_black_box
output [15:0] DOA;
output [15:0] DOB;
input [7:0] ADDRA;
input [15:0] DIA;
input ENA;
input CLKA;
input WEA;
input RSTA;
input [7:0] ADDRB;
input [15:0] DIB;
input ENB;
input CLKB;
input WEB;
input RSTB;
endmodule
module RAMB4_S1_S1(DOA, DOB, ADDRA, DIA, ENA, CLKA, WEA, RSTA, ADDRB, DIB, ENB, CLKB, WEB, RSTB); // synthesis syn_black_box
output [0:0] DOA;
output [0:0] DOB;
input [11:0] ADDRA;
input [0:0] DIA;
input ENA;
input CLKA;
input WEA;
input RSTA;
input [11:0] ADDRB;
input [0:0] DIB;
input ENB;
input CLKB;
input WEB;
input RSTB;
endmodule
module RAMB4_S1_S16(DOA, DOB, ADDRA, DIA, ENA, CLKA, WEA, RSTA, ADDRB, DIB, ENB, CLKB, WEB, RSTB); // synthesis syn_black_box
output [0:0] DOA;
output [15:0] DOB;
input [11:0] ADDRA;
input [0:0] DIA;
input ENA;
input CLKA;
input WEA;
input RSTA;
input [7:0] ADDRB;
input [15:0] DIB;
input ENB;
input CLKB;
input WEB;
input RSTB;
endmodule
module RAMB4_S1_S2(DOA, DOB, ADDRA, DIA, ENA, CLKA, WEA, RSTA, ADDRB, DIB, ENB, CLKB, WEB, RSTB); // synthesis syn_black_box
output [0:0] DOA;
output [1:0] DOB;
input [11:0] ADDRA;
input [0:0] DIA;
input ENA;
input CLKA;
input WEA;
input RSTA;
input [10:0] ADDRB;
input [1:0] DIB;
input ENB;
input CLKB;
input WEB;
input RSTB;
endmodule
module RAMB4_S1_S4(DOA, DOB, ADDRA, DIA, ENA, CLKA, WEA, RSTA, ADDRB, DIB, ENB, CLKB, WEB, RSTB); // synthesis syn_black_box
output [0:0] DOA;
output [3:0] DOB;
input [11:0] ADDRA;
input [0:0] DIA;
input ENA;
input CLKA;
input WEA;
input RSTA;
input [9:0] ADDRB;
input [3:0] DIB;
input ENB;
input CLKB;
input WEB;
input RSTB;
endmodule
module RAMB4_S1_S8(DOA, DOB, ADDRA, DIA, ENA, CLKA, WEA, RSTA, ADDRB, DIB, ENB, CLKB, WEB, RSTB); // synthesis syn_black_box
output [0:0] DOA;
output [7:0] DOB;
input [11:0] ADDRA;
input [0:0] DIA;
input ENA;
input CLKA;
input WEA;
input RSTA;
input [8:0] ADDRB;
input [7:0] DIB;
input ENB;
input CLKB;
input WEB;
input RSTB;
endmodule
module RAMB4_S2(DO, ADDR, DI, EN, CLK, WE, RST); // synthesis syn_black_box
output [1:0] DO;
input [10:0] ADDR;
input [1:0] DI;
input EN;
input CLK;
input WE;
input RST;
endmodule
module RAMB4_S2_S16(DOA, DOB, ADDRA, DIA, ENA, CLKA, WEA, RSTA, ADDRB, DIB, ENB, CLKB, WEB, RSTB); // synthesis syn_black_box
output [1:0] DOA;
output [15:0] DOB;
input [10:0] ADDRA;
input [1:0] DIA;
input ENA;
input CLKA;
input WEA;
input RSTA;
input [7:0] ADDRB;
input [15:0] DIB;
input ENB;
input CLKB;
input WEB;
input RSTB;
endmodule
module RAMB4_S2_S2(DOA, DOB, ADDRA, DIA, ENA, CLKA, WEA, RSTA, ADDRB, DIB, ENB, CLKB, WEB, RSTB); // synthesis syn_black_box
output [1:0] DOA;
output [1:0] DOB;
input [10:0] ADDRA;
input [1:0] DIA;
input ENA;
input CLKA;
input WEA;
input RSTA;
input [10:0] ADDRB;
input [1:0] DIB;
input ENB;
input CLKB;
input WEB;
input RSTB;
endmodule
module RAMB4_S2_S4(DOA, DOB, ADDRA, DIA, ENA, CLKA, WEA, RSTA, ADDRB, DIB, ENB, CLKB, WEB, RSTB); // synthesis syn_black_box
output [1:0] DOA;
output [3:0] DOB;
input [10:0] ADDRA;
input [1:0] DIA;
input ENA;
input CLKA;
input WEA;
input RSTA;
input [9:0] ADDRB;
input [3:0] DIB;
input ENB;
input CLKB;
input WEB;
input RSTB;
endmodule
module RAMB4_S2_S8(DOA, DOB, ADDRA, DIA, ENA, CLKA, WEA, RSTA, ADDRB, DIB, ENB, CLKB, WEB, RSTB); // synthesis syn_black_box
output [1:0] DOA;
output [7:0] DOB;
input [10:0] ADDRA;
input [1:0] DIA;
input ENA;
input CLKA;
input WEA;
input RSTA;
input [8:0] ADDRB;
input [7:0] DIB;
input ENB;
input CLKB;
input WEB;
input RSTB;
endmodule
module RAMB4_S4(DO, ADDR, DI, EN, CLK, WE, RST); // synthesis syn_black_box
output [3:0] DO;
input [9:0] ADDR;
input [3:0] DI;
input EN;
input CLK;
input WE;
input RST;
endmodule
module RAMB4_S4_S16(DOA, DOB, ADDRA, DIA, ENA, CLKA, WEA, RSTA, ADDRB, DIB, ENB, CLKB, WEB, RSTB); // synthesis syn_black_box
output [3:0] DOA;
output [15:0] DOB;
input [9:0] ADDRA;
input [3:0] DIA;
input ENA;
input CLKA;
input WEA;
input RSTA;
input [7:0] ADDRB;
input [15:0] DIB;
input ENB;
input CLKB;
input WEB;
input RSTB;
endmodule
module RAMB4_S4_S4(DOA, DOB, ADDRA, DIA, ENA, CLKA, WEA, RSTA, ADDRB, DIB, ENB, CLKB, WEB, RSTB); // synthesis syn_black_box
output [3:0] DOA;
output [3:0] DOB;
input [9:0] ADDRA;
input [3:0] DIA;
input ENA;
input CLKA;
input WEA;
input RSTA;
input [9:0] ADDRB;
input [3:0] DIB;
input ENB;
input CLKB;
input WEB;
input RSTB;
endmodule
module RAMB4_S4_S8(DOA, DOB, ADDRA, DIA, ENA, CLKA, WEA, RSTA, ADDRB, DIB, ENB, CLKB, WEB, RSTB); // synthesis syn_black_box
output [3:0] DOA;
output [7:0] DOB;
input [9:0] ADDRA;
input [3:0] DIA;
input ENA;
input CLKA;
input WEA;
input RSTA;
input [8:0] ADDRB;
input [7:0] DIB;
input ENB;
input CLKB;
input WEB;
input RSTB;
endmodule
module RAMB4_S8(DO, ADDR, DI, EN, CLK, WE, RST); // synthesis syn_black_box
output [7:0] DO;
input [8:0] ADDR;
input [7:0] DI;
input EN;
input CLK;
input WE;
input RST;
endmodule
module RAMB4_S8_S16(DOA, DOB, ADDRA, DIA, ENA, CLKA, WEA, RSTA, ADDRB, DIB, ENB, CLKB, WEB, RSTB); // synthesis syn_black_box
output [7:0] DOA;
output [15:0] DOB;
input [8:0] ADDRA;
input [7:0] DIA;
input ENA;
input CLKA;
input WEA;
input RSTA;
input [7:0] ADDRB;
input [15:0] DIB;
input ENB;
input CLKB;
input WEB;
input RSTB;
endmodule
module RAMB4_S8_S8(DOA, DOB, ADDRA, DIA, ENA, CLKA, WEA, RSTA, ADDRB, DIB, ENB, CLKB, WEB, RSTB); // synthesis syn_black_box
output [7:0] DOA;
output [7:0] DOB;
input [8:0] ADDRA;
input [7:0] DIA;
input ENA;
input CLKA;
input WEA;
input RSTA;
input [8:0] ADDRB;
input [7:0] DIB;
input ENB;
input CLKB;
input WEB;
input RSTB;
endmodule
module ROC(O); // synthesis syn_black_box .noprune = 1
output O;
endmodule
module SRL16(Q, A0, A1, A2, A3, CLK, D); // synthesis syn_black_box
output Q;
input A0;
input A1;
input A2;
input A3;
input CLK;
input D;
endmodule
module SRL16E(Q, A0, A1, A2, A3, CE, CLK, D); // synthesis syn_black_box
output Q;
input A0;
input A1;
input A2;
input A3;
input CE;
input CLK;
input D;
endmodule
module SRL16E_1(Q, A0, A1, A2, A3, CE, CLK, D); // synthesis syn_black_box
output Q;
input A0;
input A1;
input A2;
input A3;
input CE;
input CLK;
input D;
endmodule
module SRL16_1(Q, A0, A1, A2, A3, CLK, D); // synthesis syn_black_box
output Q;
input A0;
input A1;
input A2;
input A3;
input CLK;
input D;
endmodule
module VCC(P); // synthesis syn_black_box .noprune = 1
output P;
endmodule
module XORCY(O, CI, LI); // synthesis syn_black_box
output O;
input CI;
input LI;
endmodule
module XORCY_D(O, LO, CI, LI); // synthesis syn_black_box
output O;
output LO;
input CI;
input LI;
endmodule
module XORCY_L(LO, CI, LI); // synthesis syn_black_box
output LO;
input CI;
input LI;
endmodule
module STARTUP_VIRTEX_CLK (CLK)
/* synthesis syn_black_box .noprune=1 xc_alias="STARTUP_VIRTEX"*/ ;
    input  CLK;
endmodule
module STARTUP_VIRTEX_GSR (GSR) /* synthesis syn_black_box .noprune=1 */;
    input  GSR;
endmodule
module STARTUP_VIRTEX_GTS (GTS) /* synthesis syn_black_box .noprune=1 xc_alias="STARTUP_VIRTEX"*/;
    input  GTS;
endmodule
module STARTUP_VIRTEX_ALL(GSR, GTS, CLK)
/* synthesis syn_black_box .noprune=1 xc_alias="STARTUP_VIRTEX" */ ;
input GSR /* synthesis syn_defaultvalue=0 */,
      GTS /* synthesis syn_defaultvalue=0 */,
      CLK /* synthesis syn_defaultvalue=0 */;
endmodule
module STARTUP_VIRTEX(GSR, GTS, CLK)
/* synthesis .noprune=1 */;
input GSR /* synthesis syn_defaultvalue=0 */,
      GTS /* synthesis syn_defaultvalue=0 */,
      CLK /* synthesis syn_defaultvalue=0 */;
STARTUP_VIRTEX_GSR gsr( GSR );
STARTUP_VIRTEX_GTS gts( GTS );
STARTUP_VIRTEX_CLK clk(.CLK(CLK));
endmodule