coolrunner2.vhd

Xilinx Ise 官方源代码盘 第四章

   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of OR5B2 : component is true;
component OR5B3
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of OR5B3 : component is true;
component OR5B4
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of OR5B4 : component is true;
component OR5B5
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of OR5B5 : component is true;
component OR6
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic;
   I5 : in std_logic
 );
end component;
attribute syn_black_box of OR6 : component is true;
component OR7
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic;
   I5 : in std_logic;
   I6 : in std_logic
 );
end component;
attribute syn_black_box of OR7 : component is true;
component OR8
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic;
   I5 : in std_logic;
   I6 : in std_logic;
   I7 : in std_logic
 );
end component;
attribute syn_black_box of OR8 : component is true;
component OR9
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic;
   I5 : in std_logic;
   I6 : in std_logic;
   I7 : in std_logic;
   I8 : in std_logic
 );
end component;
attribute syn_black_box of OR9 : component is true;
component VCC
 port (
   P : out std_logic
 );
end component;
attribute syn_black_box of VCC : component is true;
attribute syn_noprune of VCC : component is true;
component XNOR2
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic
 );
end component;
attribute syn_black_box of XNOR2 : component is true;
component XNOR3
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic
 );
end component;
attribute syn_black_box of XNOR3 : component is true;
component XNOR4
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of XNOR4 : component is true;
component XOR2
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic
 );
end component;
attribute syn_black_box of XOR2 : component is true;
component XOR3
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic
 );
end component;
attribute syn_black_box of XOR3 : component is true;
component XOR4
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of XOR4 : component is true;
component XOR5
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of XOR5 : component is true;
component XOR6
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic;
   I5 : in std_logic
 );
end component;
attribute syn_black_box of XOR6 : component is true;
component XOR7
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic;
   I5 : in std_logic;
   I6 : in std_logic
 );
end component;
attribute syn_black_box of XOR7 : component is true;
component XOR8
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic;
   I5 : in std_logic;
   I6 : in std_logic;
   I7 : in std_logic
 );
end component;
attribute syn_black_box of XOR8 : component is true;

component CLK_DIV2
	port (
		CLKIN : in std_logic;
		CLKDV : out std_logic
	);
end component;
attribute syn_black_box of CLK_DIV2 : component is true;
component CLK_DIV4
	port (
		CLKIN : in std_logic;
		CLKDV : out std_logic
	);
end component;
attribute syn_black_box of CLK_DIV4 : component is true;
component CLK_DIV6
	port (
		CLKIN : in std_logic;
		CLKDV : out std_logic
	);
end component;
attribute syn_black_box of CLK_DIV6 : component is true;
component CLK_DIV8
	port (
		CLKIN : in std_logic;
		CLKDV : out std_logic
	);
end component;
attribute syn_black_box of CLK_DIV8 : component is true;
component CLK_DIV10
	port (
		CLKIN : in std_logic;
		CLKDV : out std_logic
	);
end component;
attribute syn_black_box of CLK_DIV10 : component is true;
component CLK_DIV12
	port (
		CLKIN : in std_logic;
		CLKDV : out std_logic
	);
end component;
attribute syn_black_box of CLK_DIV12 : component is true;
component CLK_DIV14
	port (
		CLKIN : in std_logic;
		CLKDV : out std_logic
	);
end component;
attribute syn_black_box of CLK_DIV14 : component is true;
component CLK_DIV16
	port (
		CLKIN : in std_logic;
		CLKDV : out std_logic
	);
end component;
attribute syn_black_box of CLK_DIV16 : component is true;

component CLK_DIV2R
	port (
		CLKIN : in std_logic;
		CLKDV : out std_logic
	);
end component;
attribute syn_black_box of CLK_DIV2R : component is true;
component CLK_DIV4R
	port (
		CLKIN : in std_logic;
		CLKDV : out std_logic
	);
end component;
attribute syn_black_box of CLK_DIV4R : component is true;
component CLK_DIV6R
	port (
		CLKIN : in std_logic;
		CLKDV : out std_logic
	);
end component;
attribute syn_black_box of CLK_DIV6R : component is true;
component CLK_DIV8R
	port (
		CLKIN : in std_logic;
		CLKDV : out std_logic
	);
end component;
attribute syn_black_box of CLK_DIV8R : component is true;
component CLK_DIV10R
	port (
		CLKIN : in std_logic;
		CLKDV : out std_logic
	);
end component;
attribute syn_black_box of CLK_DIV10R : component is true;
component CLK_DIV12R
	port (
		CLKIN : in std_logic;
		CLKDV : out std_logic
	);
end component;
attribute syn_black_box of CLK_DIV12R : component is true;
component CLK_DIV14R
	port (
		CLKIN : in std_logic;
		CLKDV : out std_logic
	);
end component;
attribute syn_black_box of CLK_DIV14R : component is true;
component CLK_DIV16R
	port (
		CLKIN : in std_logic;
		CLKDV : out std_logic
	);
end component;
attribute syn_black_box of CLK_DIV16R : component is true;

component CLK_DIV2RSD
	port (
		CLKIN : in std_logic;
		CLKDV : out std_logic
	);
end component;
attribute syn_black_box of CLK_DIV2RSD : component is true;
component CLK_DIV4RSD
	port (
		CLKIN : in std_logic;
		CLKDV : out std_logic
	);
end component;
attribute syn_black_box of CLK_DIV4RSD : component is true;
component CLK_DIV6RSD
	port (
		CLKIN : in std_logic;
		CLKDV : out std_logic
	);
end component;
attribute syn_black_box of CLK_DIV6RSD : component is true;
component CLK_DIV8RSD
	port (
		CLKIN : in std_logic;
		CLKDV : out std_logic
	);
end component;
attribute syn_black_box of CLK_DIV8RSD : component is true;
component CLK_DIV10RSD
	port (
		CLKIN : in std_logic;
		CLKDV : out std_logic
	);
end component;
attribute syn_black_box of CLK_DIV10RSD : component is true;
component CLK_DIV12RSD
	port (
		CLKIN : in std_logic;
		CLKDV : out std_logic
	);
end component;
attribute syn_black_box of CLK_DIV12RSD : component is true;
component CLK_DIV14RSD
	port (
		CLKIN : in std_logic;
		CLKDV : out std_logic
	);
end component;
attribute syn_black_box of CLK_DIV14RSD : component is true;
component CLK_DIV16RSD
	port (
		CLKIN : in std_logic;
		CLKDV : out std_logic
	);
end component;
attribute syn_black_box of CLK_DIV16RSD : component is true;

component CLK_DIV2SD
	port (
		CLKIN : in std_logic;
		CLKDV : out std_logic
	);
end component;
attribute syn_black_box of CLK_DIV2SD : component is true;
component CLK_DIV4SD
	port (
		CLKIN : in std_logic;
		CLKDV : out std_logic
	);
end component;
attribute syn_black_box of CLK_DIV4SD : component is true;
component CLK_DIV6SD
	port (
		CLKIN : in std_logic;
		CLKDV : out std_logic
	);
end component;
attribute syn_black_box of CLK_DIV6SD : component is true;
component CLK_DIV8SD
	port (
		CLKIN : in std_logic;
		CLKDV : out std_logic
	);
end component;
attribute syn_black_box of CLK_DIV8SD : component is true;
component CLK_DIV10SD
	port (
		CLKIN : in std_logic;
		CLKDV : out std_logic
	);
end component;
attribute syn_black_box of CLK_DIV10SD : component is true;
component CLK_DIV12SD
	port (
		CLKIN : in std_logic;
		CLKDV : out std_logic
	);
end component;
attribute syn_black_box of CLK_DIV12SD : component is true;
component CLK_DIV14SD
	port (
		CLKIN : in std_logic;
		CLKDV : out std_logic
	);
end component;
attribute syn_black_box of CLK_DIV14SD : component is true;
component CLK_DIV16SD
	port (
		CLKIN : in std_logic;
		CLKDV : out std_logic
	);
end component;
attribute syn_black_box of CLK_DIV16SD : component is true;

component FDDCE
	port (
		D : in std_logic;
		CE : in std_logic;
		C : in std_logic;
		CLR : in std_logic;
		Q : out std_logic
	);
end component;
attribute syn_black_box of FDDCE : component is true;

component FDDCP
	port (
		PRE : in std_logic;
		D : in std_logic;
		C : in std_logic;
		CLR : in std_logic;
		Q : out std_logic
	);
end component;
attribute syn_black_box of FDDCP : component is true;

component FDDCPE
	port (
		PRE : in std_logic;
		D : in std_logic;
		CE : in std_logic;
		C : in std_logic;
		CLR : in std_logic;
		Q : out std_logic
    );
end component;
attribute syn_black_box of FDDCPE : component is true;

component FDDP 
	port (
		PRE : in std_logic;
		D : in std_logic;
		C : in std_logic;
		Q : out std_logic
	);
end component;
attribute syn_black_box of FDDP : component is true;

component FDDPE 
	port (
		PRE : in std_logic;
		D : in std_logic;
		CE : in std_logic;
		C : in std_logic;
		Q : out std_logic
	);
end component;
attribute syn_black_box of FDDPE : component is true;

end package components;