coolrunner2.vhd

Xilinx Ise 官方源代码盘 第四章

library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
package components is
   
	attribute syn_black_box: boolean;
	attribute black_box_pad: boolean;
	attribute black_box_pad_pin: string;
	attribute black_box_tri_pins : string;
	attribute xc_props: string;
	attribute syn_noprune: boolean;
	attribute xc_padmacro : boolean;
	
	attribute syn_black_box of components : package is true;

component AND2
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic
 );
end component;
attribute syn_black_box of AND2 : component is true;
component AND2B1
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic
 );
end component;
attribute syn_black_box of AND2B1 : component is true;
component AND2B2
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic
 );
end component;
attribute syn_black_box of AND2B2 : component is true;
component AND3
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic
 );
end component;
attribute syn_black_box of AND3 : component is true;
component AND3B1
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic
 );
end component;
attribute syn_black_box of AND3B1 : component is true;
component AND3B2
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic
 );
end component;
attribute syn_black_box of AND3B2 : component is true;
component AND3B3
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic
 );
end component;
attribute syn_black_box of AND3B3 : component is true;
component AND4
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of AND4 : component is true;
component AND4B1
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of AND4B1 : component is true;
component AND4B2
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of AND4B2 : component is true;
component AND4B3
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of AND4B3 : component is true;
component AND4B4
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of AND4B4 : component is true;
component AND5
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of AND5 : component is true;
component AND5B1
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of AND5B1 : component is true;
component AND5B2
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of AND5B2 : component is true;
component AND5B3
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of AND5B3 : component is true;
component AND5B4
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of AND5B4 : component is true;
component AND5B5
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of AND5B5 : component is true;
component AND6
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic;
   I5 : in std_logic
 );
end component;
attribute syn_black_box of AND6 : component is true;
component AND7
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic;
   I5 : in std_logic;
   I6 : in std_logic
 );
end component;
attribute syn_black_box of AND7 : component is true;
component AND8
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic;
   I5 : in std_logic;
   I6 : in std_logic;
   I7 : in std_logic
 );
end component;
attribute syn_black_box of AND8 : component is true;
component AND9
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic;
   I5 : in std_logic;
   I6 : in std_logic;
   I7 : in std_logic;
   I8 : in std_logic
 );
end component;
attribute syn_black_box of AND9 : component is true;
component BUF
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of BUF : component is true;
--BUFE is not supported for the XC9500XLK and XC9500XV devices.
component BUFE
 port (
   O : out std_logic;
   I : in std_logic;
   E : in std_logic
 );
end component;
attribute syn_black_box of BUFE : component is true;
attribute black_box_tri_pins of BUFE : component is "O";
component BUFG
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of BUFG : component is true;
attribute black_box_pad_pin of BUFG : component is "I";
component BUFGSR
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of BUFGSR : component is true;
attribute black_box_pad_pin of BUFGSR : component is "I";
component BUFGTS
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of BUFGTS : component is true;
attribute black_box_pad_pin of BUFGTS : component is "I";
--BUFT is not supported for the XC9500XL and XC9500XV devices
component BUFT
 port (
   O : out std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of BUFT : component is true;
attribute black_box_tri_pins of BUFT : component is "O";
component FDCE
 port (
   Q : out std_logic;
   C : in std_logic;
   CE : in std_logic;
   CLR : in std_logic;
   D : in std_logic
 );
end component;
attribute syn_black_box of FDCE : component is true;
component FDCP
 port (
   Q : out std_logic;
   C : in std_logic;
   CLR : in std_logic;
   D : in std_logic;
   PRE : in std_logic
 );
end component;
attribute syn_black_box of FDCP : component is true;
component FDPE
 port (
   Q : out std_logic;
   C : in std_logic;
   CE : in std_logic;
   D : in std_logic;
   PRE : in std_logic
 );
end component;
attribute syn_black_box of FDPE : component is true;
component FTCP
 port (
   Q : out std_logic;
   C : in std_logic;
   CLR : in std_logic;
   PRE : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of FTCP : component is true;
component GND
 port (
   G : out std_logic
 );
end component;
attribute syn_black_box of GND : component is true;
attribute syn_noprune of GND : component is true;
component IBUF
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF : component is true;
attribute black_box_pad_pin of IBUF : component is "I";
component INV
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of INV : component is true;
component NAND2
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic
 );
end component;
attribute syn_black_box of NAND2 : component is true;
component NAND2B1
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic
 );
end component;
attribute syn_black_box of NAND2B1 : component is true;
component NAND2B2
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic
 );
end component;
attribute syn_black_box of NAND2B2 : component is true;
component NAND3
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic
 );
end component;
attribute syn_black_box of NAND3 : component is true;
component NAND3B1
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic
 );
end component;
attribute syn_black_box of NAND3B1 : component is true;
component NAND3B2
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic
 );
end component;
attribute syn_black_box of NAND3B2 : component is true;
component NAND3B3
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic
 );
end component;
attribute syn_black_box of NAND3B3 : component is true;
component NAND4
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of NAND4 : component is true;
component NAND4B1
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of NAND4B1 : component is true;
component NAND4B2
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of NAND4B2 : component is true;
component NAND4B3
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute syn_black_box of NAND4B3 : component is true;
component NAND4B4
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic
 );
end component;
attribute black_box of NAND4B4 : component is true;
component NAND5
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of NAND5 : component is true;
component NAND5B1
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic;
   I2 : in std_logic;
   I3 : in std_logic;
   I4 : in std_logic
 );
end component;
attribute syn_black_box of NAND5B1 : component is true;
component NAND5B2