virtexe.vhd

Xilinx Ise 官方源代码盘 第四章

 port (
   O : out std_logic;
   A0 : in std_logic;
   A1 : in std_logic;
   A2 : in std_logic;
   A3 : in std_logic
 );
end component;
attribute syn_black_box of ROM16X1 : component is true;
component ROM32X1
  generic (INIT : bit_vector := X"00000000");
 port (
   O : out std_logic;
   A0 : in std_logic;
   A1 : in std_logic;
   A2 : in std_logic;
   A3 : in std_logic;
   A4 : in std_logic
 );
end component;
attribute syn_black_box of ROM32X1 : component is true;
component RAMB4_S1
 port (
   DO : out std_logic_vector (0 downto 0);
   ADDR : in std_logic_vector (11 downto 0);
   DI : in std_logic_vector (0 downto 0);
   EN : in std_logic;
   CLK : in std_logic;
   WE : in std_logic;
   RST : in std_logic
 );
end component;
attribute syn_black_box of RAMB4_S1 : component is true;
component RAMB4_S16
 port (
   DO : out std_logic_vector (15 downto 0);
   ADDR : in std_logic_vector (7 downto 0);
   DI : in std_logic_vector (15 downto 0);
   EN : in std_logic;
   CLK : in std_logic;
   WE : in std_logic;
   RST : in std_logic
 );
end component;
attribute syn_black_box of RAMB4_S16 : component is true;
component RAMB4_S16_S16
 port (
   DOA : out std_logic_vector (15 downto 0);
   DOB : out std_logic_vector (15 downto 0);
   ADDRA : in std_logic_vector (7 downto 0);
   DIA : in std_logic_vector (15 downto 0);
   ENA : in std_logic;
   CLKA : in std_logic;
   WEA : in std_logic;
   RSTA : in std_logic;
   ADDRB : in std_logic_vector (7 downto 0);
   DIB : in std_logic_vector (15 downto 0);
   ENB : in std_logic;
   CLKB : in std_logic;
   WEB : in std_logic;
   RSTB : in std_logic
 );
end component;
attribute syn_black_box of RAMB4_S16_S16 : component is true;
component RAMB4_S1_S1
 port (
   DOA : out std_logic_vector (0 downto 0);
   DOB : out std_logic_vector (0 downto 0);
   ADDRA : in std_logic_vector (11 downto 0);
   DIA : in std_logic_vector (0 downto 0);
   ENA : in std_logic;
   CLKA : in std_logic;
   WEA : in std_logic;
   RSTA : in std_logic;
   ADDRB : in std_logic_vector (11 downto 0);
   DIB : in std_logic_vector (0 downto 0);
   ENB : in std_logic;
   CLKB : in std_logic;
   WEB : in std_logic;
   RSTB : in std_logic
 );
end component;
attribute syn_black_box of RAMB4_S1_S1 : component is true;
component RAMB4_S1_S16
 port (
   DOA : out std_logic_vector (0 downto 0);
   DOB : out std_logic_vector (15 downto 0);
   ADDRA : in std_logic_vector (11 downto 0);
   DIA : in std_logic_vector (0 downto 0);
   ENA : in std_logic;
   CLKA : in std_logic;
   WEA : in std_logic;
   RSTA : in std_logic;
   ADDRB : in std_logic_vector (7 downto 0);
   DIB : in std_logic_vector (15 downto 0);
   ENB : in std_logic;
   CLKB : in std_logic;
   WEB : in std_logic;
   RSTB : in std_logic
 );
end component;
attribute syn_black_box of RAMB4_S1_S16 : component is true;
component RAMB4_S1_S2
 port (
   DOA : out std_logic_vector (0 downto 0);
   DOB : out std_logic_vector (1 downto 0);
   ADDRA : in std_logic_vector (11 downto 0);
   DIA : in std_logic_vector (0 downto 0);
   ENA : in std_logic;
   CLKA : in std_logic;
   WEA : in std_logic;
   RSTA : in std_logic;
   ADDRB : in std_logic_vector (10 downto 0);
   DIB : in std_logic_vector (1 downto 0);
   ENB : in std_logic;
   CLKB : in std_logic;
   WEB : in std_logic;
   RSTB : in std_logic
 );
end component;
attribute syn_black_box of RAMB4_S1_S2 : component is true;
component RAMB4_S1_S4
 port (
   DOA : out std_logic_vector (0 downto 0);
   DOB : out std_logic_vector (3 downto 0);
   ADDRA : in std_logic_vector (11 downto 0);
   DIA : in std_logic_vector (0 downto 0);
   ENA : in std_logic;
   CLKA : in std_logic;
   WEA : in std_logic;
   RSTA : in std_logic;
   ADDRB : in std_logic_vector (9 downto 0);
   DIB : in std_logic_vector (3 downto 0);
   ENB : in std_logic;
   CLKB : in std_logic;
   WEB : in std_logic;
   RSTB : in std_logic
 );
end component;
attribute syn_black_box of RAMB4_S1_S4 : component is true;
component RAMB4_S1_S8
 port (
   DOA : out std_logic_vector (0 downto 0);
   DOB : out std_logic_vector (7 downto 0);
   ADDRA : in std_logic_vector (11 downto 0);
   DIA : in std_logic_vector (0 downto 0);
   ENA : in std_logic;
   CLKA : in std_logic;
   WEA : in std_logic;
   RSTA : in std_logic;
   ADDRB : in std_logic_vector (8 downto 0);
   DIB : in std_logic_vector (7 downto 0);
   ENB : in std_logic;
   CLKB : in std_logic;
   WEB : in std_logic;
   RSTB : in std_logic
 );
end component;
attribute syn_black_box of RAMB4_S1_S8 : component is true;
component RAMB4_S2
 port (
   DO : out std_logic_vector (1 downto 0);
   ADDR : in std_logic_vector (10 downto 0);
   DI : in std_logic_vector (1 downto 0);
   EN : in std_logic;
   CLK : in std_logic;
   WE : in std_logic;
   RST : in std_logic
 );
end component;
attribute syn_black_box of RAMB4_S2 : component is true;
component RAMB4_S2_S16
 port (
   DOA : out std_logic_vector (1 downto 0);
   DOB : out std_logic_vector (15 downto 0);
   ADDRA : in std_logic_vector (10 downto 0);
   DIA : in std_logic_vector (1 downto 0);
   ENA : in std_logic;
   CLKA : in std_logic;
   WEA : in std_logic;
   RSTA : in std_logic;
   ADDRB : in std_logic_vector (7 downto 0);
   DIB : in std_logic_vector (15 downto 0);
   ENB : in std_logic;
   CLKB : in std_logic;
   WEB : in std_logic;
   RSTB : in std_logic
 );
end component;
attribute syn_black_box of RAMB4_S2_S16 : component is true;
component RAMB4_S2_S2
 port (
   DOA : out std_logic_vector (1 downto 0);
   DOB : out std_logic_vector (1 downto 0);
   ADDRA : in std_logic_vector (10 downto 0);
   DIA : in std_logic_vector (1 downto 0);
   ENA : in std_logic;
   CLKA : in std_logic;
   WEA : in std_logic;
   RSTA : in std_logic;
   ADDRB : in std_logic_vector (10 downto 0);
   DIB : in std_logic_vector (1 downto 0);
   ENB : in std_logic;
   CLKB : in std_logic;
   WEB : in std_logic;
   RSTB : in std_logic
 );
end component;
attribute syn_black_box of RAMB4_S2_S2 : component is true;
component RAMB4_S2_S4
 port (
   DOA : out std_logic_vector (1 downto 0);
   DOB : out std_logic_vector (3 downto 0);
   ADDRA : in std_logic_vector (10 downto 0);
   DIA : in std_logic_vector (1 downto 0);
   ENA : in std_logic;
   CLKA : in std_logic;
   WEA : in std_logic;
   RSTA : in std_logic;
   ADDRB : in std_logic_vector (9 downto 0);
   DIB : in std_logic_vector (3 downto 0);
   ENB : in std_logic;
   CLKB : in std_logic;
   WEB : in std_logic;
   RSTB : in std_logic
 );
end component;
attribute syn_black_box of RAMB4_S2_S4 : component is true;
component RAMB4_S2_S8
 port (
   DOA : out std_logic_vector (1 downto 0);
   DOB : out std_logic_vector (7 downto 0);
   ADDRA : in std_logic_vector (10 downto 0);
   DIA : in std_logic_vector (1 downto 0);
   ENA : in std_logic;
   CLKA : in std_logic;
   WEA : in std_logic;
   RSTA : in std_logic;
   ADDRB : in std_logic_vector (8 downto 0);
   DIB : in std_logic_vector (7 downto 0);
   ENB : in std_logic;
   CLKB : in std_logic;
   WEB : in std_logic;
   RSTB : in std_logic
 );
end component;
attribute syn_black_box of RAMB4_S2_S8 : component is true;
component RAMB4_S4
 port (
   DO : out std_logic_vector (3 downto 0);
   ADDR : in std_logic_vector (9 downto 0);
   DI : in std_logic_vector (3 downto 0);
   EN : in std_logic;
   CLK : in std_logic;
   WE : in std_logic;
   RST : in std_logic
 );
end component;
attribute syn_black_box of RAMB4_S4 : component is true;
component RAMB4_S4_S16
 port (
   DOA : out std_logic_vector (3 downto 0);
   DOB : out std_logic_vector (15 downto 0);
   ADDRA : in std_logic_vector (9 downto 0);
   DIA : in std_logic_vector (3 downto 0);
   ENA : in std_logic;
   CLKA : in std_logic;
   WEA : in std_logic;
   RSTA : in std_logic;
   ADDRB : in std_logic_vector (7 downto 0);
   DIB : in std_logic_vector (15 downto 0);
   ENB : in std_logic;
   CLKB : in std_logic;
   WEB : in std_logic;
   RSTB : in std_logic
 );
end component;
attribute syn_black_box of RAMB4_S4_S16 : component is true;
component RAMB4_S4_S4
 port (
   DOA : out std_logic_vector (3 downto 0);
   DOB : out std_logic_vector (3 downto 0);
   ADDRA : in std_logic_vector (9 downto 0);
   DIA : in std_logic_vector (3 downto 0);
   ENA : in std_logic;
   CLKA : in std_logic;
   WEA : in std_logic;
   RSTA : in std_logic;
   ADDRB : in std_logic_vector (9 downto 0);
   DIB : in std_logic_vector (3 downto 0);
   ENB : in std_logic;
   CLKB : in std_logic;
   WEB : in std_logic;
   RSTB : in std_logic
 );
end component;
attribute syn_black_box of RAMB4_S4_S4 : component is true;
component RAMB4_S4_S8
 port (
   DOA : out std_logic_vector (3 downto 0);
   DOB : out std_logic_vector (7 downto 0);
   ADDRA : in std_logic_vector (9 downto 0);
   DIA : in std_logic_vector (3 downto 0);
   ENA : in std_logic;
   CLKA : in std_logic;
   WEA : in std_logic;
   RSTA : in std_logic;
   ADDRB : in std_logic_vector (8 downto 0);
   DIB : in std_logic_vector (7 downto 0);
   ENB : in std_logic;
   CLKB : in std_logic;
   WEB : in std_logic;
   RSTB : in std_logic
 );
end component;
attribute syn_black_box of RAMB4_S4_S8 : component is true;
component RAMB4_S8
 port (
   DO : out std_logic_vector (7 downto 0);
   ADDR : in std_logic_vector (8 downto 0);
   DI : in std_logic_vector (7 downto 0);
   EN : in std_logic;
   CLK : in std_logic;
   WE : in std_logic;
   RST : in std_logic
 );
end component;
attribute syn_black_box of RAMB4_S8 : component is true;
component RAMB4_S8_S16
 port (
   DOA : out std_logic_vector (7 downto 0);
   DOB : out std_logic_vector (15 downto 0);
   ADDRA : in std_logic_vector (8 downto 0);
   DIA : in std_logic_vector (7 downto 0);
   ENA : in std_logic;
   CLKA : in std_logic;
   WEA : in std_logic;
   RSTA : in std_logic;
   ADDRB : in std_logic_vector (7 downto 0);
   DIB : in std_logic_vector (15 downto 0);
   ENB : in std_logic;
   CLKB : in std_logic;
   WEB : in std_logic;
   RSTB : in std_logic
 );
end component;
attribute syn_black_box of RAMB4_S8_S16 : component is true;
component RAMB4_S8_S8
 port (
   DOA : out std_logic_vector (7 downto 0);
   DOB : out std_logic_vector (7 downto 0);
   ADDRA : in std_logic_vector (8 downto 0);
   DIA : in std_logic_vector (7 downto 0);
   ENA : in std_logic;
   CLKA : in std_logic;
   WEA : in std_logic;
   RSTA : in std_logic;
   ADDRB : in std_logic_vector (8 downto 0);
   DIB : in std_logic_vector (7 downto 0);
   ENB : in std_logic;
   CLKB : in std_logic;
   WEB : in std_logic;
   RSTB : in std_logic
 );
end component;
attribute syn_black_box of RAMB4_S8_S8 : component is true;
component ROC
 port (
   O : out std_logic
 );
end component;
attribute syn_black_box of ROC : component is true;
attribute syn_noprune of ROC : component is true;
component SRL16
 port (
   Q : out std_logic;
   A0 : in std_logic;
   A1 : in std_logic;
   A2 : in std_logic;
   A3 : in std_logic;
   CLK : in std_logic;
   D : in std_logic
 );
end component;
attribute syn_black_box of SRL16 : component is true;
component SRL16E
 port (
   Q : out std_logic;
   A0 : in std_logic;
   A1 : in std_logic;
   A2 : in std_logic;
   A3 : in std_logic;
   CE : in std_logic;
   CLK : in std_logic;
   D : in std_logic
 );
end component;
attribute syn_black_box of SRL16E : component is true;
component SRL16E_1
 port (
   Q : out std_logic;
   A0 : in std_logic;
   A1 : in std_logic;
   A2 : in std_logic;
   A3 : in std_logic;
   CE : in std_logic;
   CLK : in std_logic;
   D : in std_logic
 );
end component;
attribute syn_black_box of SRL16E_1 : component is true;
component SRL16_1
 port (
   Q : out std_logic;
   A0 : in std_logic;
   A1 : in std_logic;
   A2 : in std_logic;
   A3 : in std_logic;
   CLK : in std_logic;
   D : in std_logic
 );
end component;
attribute syn_black_box of SRL16_1 : component is true;
component STARTBUF_VIRTEX
    port( GSRIN     : in std_ulogic;
          GTSIN     : in std_ulogic;
          CLKIN     : in std_ulogic;
          GTSOUT    : out std_ulogic);
end component;
attribute syn_black_box of STARTBUF_VIRTEX : component is true;

component STARTUP_VIRTEX
   port( GSR, GTS, CLK: in std_logic);
end component;

component STARTUP_VIRTEX_GTS
   port(GTS: in std_logic);
end component;
attribute syn_black_box of STARTUP_VIRTEX_GTS : component is true;
attribute syn_noprune of STARTUP_VIRTEX_GTS: component is true;
attribute xc_alias of STARTUP_VIRTEX_GTS : component is "STARTUP_VIRTEX";

component STARTUP_VIRTEX_GSR
   port(GSR: in std_logic);
end component;
attribute syn_black_box of STARTUP_VIRTEX_GSR : component is true;
attribute syn_noprune of STARTUP_VIRTEX_GSR: component is true;
attribute xc_alias of STARTUP_VIRTEX_GSR : component is "STARTUP_VIRTEX";

component STARTUP_VIRTEX_CLK
   port( CLK: in std_logic);
end component;
attribute syn_black_box of STARTUP_VIRTEX_CLK : component is true;
attribute syn_noprune of STARTUP_VIRTEX_CLK: component is true;
attribute xc_alias of STARTUP_VIRTEX_CLK: component is "STARTUP_VIRTEX";

component STARTUP_VIRTEX_ALL
   port(GSR,GTS,CLK: in std_logic);
end component;
attribute syn_noprune of STARTUP_VIRTEX_ALL: component is true;
attribute xc_alias of STARTUP_VIRTEX_ALL: component is "STARTUP_VIRTEX";

component TOC
 port (
   O : out std_logic := '0'
);
end component;
attribute syn_black_box of TOC : component is true;
attribute syn_noprune of TOC : component is true;
component TOCBUF
 port (
   O : out std_logic := '0';
   I : in std_logic
);
end component;
attribute syn_black_box of TOCBUF : component is true;
component VCC
 port (
   P : out std_logic
 );
end component;
attribute syn_black_box of VCC : component is true;
attribute syn_noprune of VCC : component is true;
component XORCY
 port (
   O : out std_logic;
   CI : in std_logic;
   LI : in std_logic
 );
end component;
attribute syn_black_box of XORCY : component is true;
component XORCY_D
 port (
   O : out std_logic;
   LO : out std_logic;
   CI : in std_logic;
   LI : in std_logic
 );
end component;
attribute syn_black_box of XORCY_D : component is true;
component XORCY_L
 port (
   LO : out std_logic;
   CI : in std_logic;
   LI : in std_logic
 );
end component;
attribute syn_black_box of XORCY_L : component is true;
end package components;

library IEEE;
use IEEE.std_logic_1164.all;
library virtex;
use virtex.components.all;
entity STARTUP_VIRTEX is
   port(GSR, GTS, CLK: in std_logic := '0');
end STARTUP_VIRTEX;

architecture struct of STARTUP_VIRTEX is
attribute syn_noprune of struct : architecture is true;
begin
  gsr0 : STARTUP_VIRTEX_GSR port map ( GSR => GSR );
  gts0 : STARTUP_VIRTEX_GTS port map ( GTS => GTS );
  clk0 : STARTUP_VIRTEX_CLK port map ( CLK => CLK);
end struct;