virtexe.vhd

Xilinx Ise 官方源代码盘 第四章

 port (
   G : out std_logic
 );
end component;
attribute syn_black_box of GND : component is true;
component IBUF
 generic (
   IOSTANDARD : string := "default"
 );
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF : component is true;
component IBUFG
 generic (
   IOSTANDARD : string := "default"
 );
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG : component is true;
attribute black_box_pad_pin of IBUFG : component is "I";
component IBUFG_AGP
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_AGP : component is true;
component IBUFG_CTT
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_CTT : component is true;
component IBUFG_GTL
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_GTL : component is true;
component IBUFG_GTLP
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_GTLP : component is true;
component IBUFG_HSTL_I
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_HSTL_I : component is true;
component IBUFG_HSTL_III
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_HSTL_III : component is true;
component IBUFG_HSTL_IV
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_HSTL_IV : component is true;
component IBUFG_LVCMOS18
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_LVCMOS18 : component is true;
component IBUFG_LVCMOS2
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_LVCMOS2 : component is true;
component IBUFG_LVDS
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_LVDS : component is true;
component IBUFG_LVPECL
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_LVPECL : component is true;
component IBUFG_PCI33_3
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_PCI33_3 : component is true;
component IBUFG_PCI66_3
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_PCI66_3 : component is true;
component IBUFG_SSTL2_I
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_SSTL2_I : component is true;
component IBUFG_SSTL2_II
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_SSTL2_II : component is true;
component IBUFG_SSTL3_I
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_SSTL3_I : component is true;
component IBUFG_SSTL3_II
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUFG_SSTL3_II : component is true;
component IBUF_AGP
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_AGP : component is true;
component IBUF_CTT
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_CTT : component is true;
component IBUF_GTL
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_GTL : component is true;
component IBUF_GTLP
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_GTLP : component is true;
component IBUF_HSTL_I
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_HSTL_I : component is true;
component IBUF_HSTL_III
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_HSTL_III : component is true;
component IBUF_HSTL_IV
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_HSTL_IV : component is true;
component IBUF_LVCMOS18
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_LVCMOS18 : component is true;
component IBUF_LVCMOS2
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_LVCMOS2 : component is true;
component IBUF_LVDS
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_LVDS : component is true;
component IBUF_LVPECL
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_LVPECL : component is true;
component IBUF_PCI33_3
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_PCI33_3 : component is true;
component IBUF_PCI66_3
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_PCI66_3 : component is true;
component IBUF_SSTL2_I
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_SSTL2_I : component is true;
component IBUF_SSTL2_II
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_SSTL2_II : component is true;
component IBUF_SSTL3_I
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_SSTL3_I : component is true;
component IBUF_SSTL3_II
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of IBUF_SSTL3_II : component is true;
component INV
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of INV : component is true;
component IOBUF
 generic (
   IOSTANDARD : string := "default";
   SLEW : string := "SLOW";
   DRIVE : integer := 12
 );
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF : component is true;
component IOBUF_AGP
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_AGP : component is true;
component IOBUF_CTT
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_CTT : component is true;
component IOBUF_F_12
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_F_12 : component is true;
component IOBUF_F_16
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_F_16 : component is true;
component IOBUF_F_2
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_F_2 : component is true;
component IOBUF_F_24
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_F_24 : component is true;
component IOBUF_F_4
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_F_4 : component is true;
component IOBUF_F_6
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_F_6 : component is true;
component IOBUF_F_8
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_F_8 : component is true;
component IOBUF_GTL
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_GTL : component is true;
component IOBUF_GTLP
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_GTLP : component is true;
component IOBUF_HSTL_I
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_HSTL_I : component is true;
component IOBUF_HSTL_III
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_HSTL_III : component is true;
component IOBUF_HSTL_IV
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_HSTL_IV : component is true;
component IOBUF_LVCMOS18
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS18 : component is true;
component IOBUF_LVCMOS2
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS2 : component is true;
component IOBUF_LVDS
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVDS : component is true;
component IOBUF_LVPECL
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVPECL : component is true;
component IOBUF_PCI33_3
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_PCI33_3 : component is true;
component IOBUF_PCI66_3
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_PCI66_3 : component is true;
component IOBUF_SSTL2_I
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_SSTL2_I : component is true;
component IOBUF_SSTL2_II
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_SSTL2_II : component is true;
component IOBUF_SSTL3_I
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_SSTL3_I : component is true;
component IOBUF_SSTL3_II
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_SSTL3_II : component is true;
component IOBUF_S_12
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_S_12 : component is true;
component IOBUF_S_16
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_S_16 : component is true;
component IOBUF_S_2
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );