xc3000.vhd

Xilinx Ise 官方源代码盘 第四章

-- VHDL Xilinx/xc3000 Import library.
-- Copyright 1995 Synplicity Inc.
library IEEE;
use IEEE.STD_LOGIC_1164.all;


package components is

attribute syn_black_box: boolean;
attribute black_box_pad: boolean;
attribute black_box_pad_pin: string;
attribute black_box_tri_pins : string;
attribute xc_alias: string;
attribute xc_props: string;
attribute synthesis_noprune: boolean;

attribute syn_black_box of components: package is true;
----- Component ACLK ----
component ACLK
   port(
      O				    : out STD_LOGIC;
      I				    : in STD_LOGIC);
end component;

---- Component CLBMAP ----
component CLBMAP
   port(
      A, B, C, D, E, K, DI, EC, RD, X, Y : in STD_LOGIC
      );
end component;
attribute synthesis_noprune of CLBMAP: component is true; 

component CLBMAP_PUC
   port(
      A, B, C, D, E, K, DI, EC, RD, X, Y : in STD_LOGIC
      );
end component;
attribute synthesis_noprune of CLBMAP_PUC: component is true; 

component CLBMAP_PLC
   port(
      A, B, C, D, E, K, DI, EC, RD, X, Y : in STD_LOGIC
      );
end component;
attribute synthesis_noprune of CLBMAP_PLC: component is true; 

component CLBMAP_PUO
   port(
      A, B, C, D, E, K, DI, EC, RD, X, Y : in STD_LOGIC
      );
end component;
attribute synthesis_noprune of CLBMAP_PUO: component is true; 

component CLBMAP_PLO
   port(
      A, B, C, D, E, K, DI, EC, RD, X, Y : in STD_LOGIC
      );
end component;
attribute synthesis_noprune of CLBMAP_PLO: component is true; 

component CLB
   port(
      A, B, C, D, E, O1, EC, K, RD : in STD_LOGIC;
      X, Y			   : out STD_LOGIC
      );
end component;

component GCLK
   port(
	O			   : out STD_LOGIC;
        I			   : in STD_LOGIC
       );
end component;

component ILD
   port(
       G, D			   : in STD_LOGIC;
       Q			   : out STD_LOGIC
       );
end component;

----- Component AND2 -----
component AND2

   port(
      O                              :	out   STD_LOGIC;
      I1                             :	in    STD_LOGIC;
      I0                             :	in    STD_LOGIC);
end component;


----- Component AND3 -----
component AND3

   port(
      O                              :	out   STD_LOGIC;
      I2                             :	in    STD_LOGIC;
      I1                             :	in    STD_LOGIC;
      I0                             :	in    STD_LOGIC);
end component;


----- Component AND4 -----
component AND4

   port(
      O                              :	out   STD_LOGIC;
      I3                             :	in    STD_LOGIC;
      I2                             :	in    STD_LOGIC;
      I1                             :	in    STD_LOGIC;
      I0                             :	in    STD_LOGIC);
end component;


----- Component AND5 -----
component AND5

   port(
      O                              :	out   STD_LOGIC;
      I4                             :	in    STD_LOGIC;
      I3                             :	in    STD_LOGIC;
      I2                             :	in    STD_LOGIC;
      I1                             :	in    STD_LOGIC;
      I0                             :	in    STD_LOGIC);
end component;


----- Component BUF -----
component BUF
   port(
      O                              :	out   STD_LOGIC;
      I                              :	in    STD_LOGIC);
end component;


----- Component BUFG -----
component BUFG
   port(
      O                              :	out   STD_LOGIC;
      I                              :	in    STD_LOGIC);
end component;

component BUFG_F
   port(
      O                              :	out   STD_LOGIC;
      I                              :	in    STD_LOGIC);
end component;

----- Component BUFT -----
component BUFT
   port(
      O                              :	out   STD_LOGIC;
      I                              :	in    STD_LOGIC;
      T                              :	in    STD_LOGIC);
end component;
attribute black_box_tri_pins of BUFT : component is "O";

----- Component FDCE -----
component FDCE
   port(
      Q                              :	out   STD_LOGIC;
      C                              :	in    STD_LOGIC;
      CE                             :	in    STD_LOGIC;
      CLR                            :	in    STD_LOGIC;
      D                              :	in    STD_LOGIC
      );
end component;


----- Component FDC -----
component FDC
   port(
      Q                              :	out   STD_LOGIC;
      C                              :	in    STD_LOGIC;
      CLR                            :	in    STD_LOGIC;
      D                              :	in    STD_LOGIC
      );
end component;


----- Component INV -----
component INV
   port(
      O                              :	out   STD_LOGIC;
      I                              :	in    STD_LOGIC);
end component;

---- Component IOBUF -----

component IOBUF
 port ( O : out std_logic;
       IO : inout std_logic;
       I,T : in std_logic
 );
end component;

component IOBUF_N_F
 port ( O : out std_logic;
       IO : inout std_logic;
       I,T : in std_logic
 );
end component;

component IOBUF_N_S
 port ( O : out std_logic;
       IO : inout std_logic;
       I,T : in std_logic
 );
end component;

----- Component FDPI ----
component FDPI
   port(
       Q			    : out STD_LOGIC;
       D, C, PRE		    : in STD_LOGIC
      );
end component;
      
----- Component FDPEI ----
component FDPEI
   port(
       Q			    : out STD_LOGIC;
       D, C, CE, PRE		    : in STD_LOGIC
       );
end component;

----- Component IBUF -----
component IBUF
   port(
      O                              :	out   STD_LOGIC;
      I                              :	in    STD_LOGIC);
end component;


component IBUF_U
   port(
      O                              :	out   STD_LOGIC;
      I                              :	in    STD_LOGIC);
end component;

component IBUF_CMOS
   port(
      O                              :	out   STD_LOGIC;
      I                              :	in    STD_LOGIC);
end component;

component IBUF_TTL
   port(
      O                              :	out   STD_LOGIC;
      I                              :	in    STD_LOGIC);
end component;

----- Component IFD -----
component IFD
   port(
      Q                              :	out   STD_LOGIC;
      D                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC
      );
end component;

component IFD_U
   port(
      Q                              :	out   STD_LOGIC;
      D                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC
      );
end component;

----- Component NAND2 -----
component NAND2
   port(
      O                              :	out   STD_LOGIC;
      I1                             :	in    STD_LOGIC;
      I0                             :	in    STD_LOGIC);
end component;


----- Component NAND3 -----
component NAND3
   port(
      O                              :	out   STD_LOGIC;
      I2                             :	in    STD_LOGIC;
      I1                             :	in    STD_LOGIC;
      I0                             :	in    STD_LOGIC);
end component;


----- Component NAND4 -----
component NAND4
   port(
      O                              :	out   STD_LOGIC;
      I3                             :	in    STD_LOGIC;
      I2                             :	in    STD_LOGIC;
      I1                             :	in    STD_LOGIC;
      I0                             :	in    STD_LOGIC);
end component;


----- Component NAND5 -----
component NAND5
   port(
      O                              :	out   STD_LOGIC;
      I4                             :	in    STD_LOGIC;
      I3                             :	in    STD_LOGIC;
      I2                             :	in    STD_LOGIC;
      I1                             :	in    STD_LOGIC;
      I0                             :	in    STD_LOGIC);
end component;


----- Component NOR2 -----
component NOR2
   port(
      O                              :	out   STD_LOGIC;
      I1                             :	in    STD_LOGIC;
      I0                             :	in    STD_LOGIC);
end component;


----- Component NOR3 -----
component NOR3
   port(
      O                              :	out   STD_LOGIC;
      I2                             :	in    STD_LOGIC;
      I1                             :	in    STD_LOGIC;
      I0                             :	in    STD_LOGIC);
end component;


----- Component NOR4 -----
component NOR4
   port(
      O                              :	out   STD_LOGIC;
      I3                             :	in    STD_LOGIC;
      I2                             :	in    STD_LOGIC;
      I1                             :	in    STD_LOGIC;
      I0                             :	in    STD_LOGIC);
end component;


----- Component NOR5 -----
component NOR5
   port(
      O                              :	out   STD_LOGIC;
      I4                             :	in    STD_LOGIC;
      I3                             :	in    STD_LOGIC;
      I2                             :	in    STD_LOGIC;
      I1                             :	in    STD_LOGIC;
      I0                             :	in    STD_LOGIC);
end component;


----- Component OBUF -----
component OBUF
   port(
      O                              :	out   STD_LOGIC;
      I                              :	in    STD_LOGIC
      );
end component;

component OBUF_F
   port(
      O                              :	out   STD_LOGIC;
      I                              :	in    STD_LOGIC
      );
end component;

component OBUF_U
   port(
      O                              :	out   STD_LOGIC;
      I                              :	in    STD_LOGIC
      );
end component;

----- Component OBUFT -----
component OBUFT
   port(
      O                              :	out   STD_LOGIC;
      I                              :	in    STD_LOGIC;
      T                              :	in    STD_LOGIC
      );
end component;

component OBUFT_S
   port(
      O                              :	out   STD_LOGIC;
      I                              :	in    STD_LOGIC;
      T                              :	in    STD_LOGIC
      );
end component;

component OBUFT_F
   port(
      O                              :	out   STD_LOGIC;
      I                              :	in    STD_LOGIC;
      T                              :	in    STD_LOGIC
      );
end component;

----- Component OFD -----
component OFD
   port(
      Q                              :	out   STD_LOGIC;
      D                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC
      );
end component;

component OFD_F
   port(
      Q                              :	out   STD_LOGIC;
      D                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC
      );
end component;

component OFD_FU
   port(
      Q                              :	out   STD_LOGIC;
      D                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC
      );
end component;

component OFD_U
   port(
      Q                              :	out   STD_LOGIC;
      D                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC
      );
end component;

----- Component OFDT -----
component OFDT
   port(
      O                              :	out   STD_LOGIC;
      D                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC;
      T                              :	in    STD_LOGIC
      );
end component;

component OFDT_F
   port(
      O                              :	out   STD_LOGIC;
      D                              :	in    STD_LOGIC;
      C                              :	in    STD_LOGIC;
      T                              :	in    STD_LOGIC
      );
end component;

----- Component OR2 -----
component OR2
   port(
      O                              :	out   STD_LOGIC;
      I1                             :	in    STD_LOGIC;
      I0                             :	in    STD_LOGIC);
end component;


----- Component OR3 -----
component OR3
   port(
      O                              :	out   STD_LOGIC;
      I2                             :	in    STD_LOGIC;
      I1                             :	in    STD_LOGIC;
      I0                             :	in    STD_LOGIC);
end component;


----- Component OR4 -----
component OR4
   port(
      O                              :	out   STD_LOGIC;
      I3                             :	in    STD_LOGIC;
      I2                             :	in    STD_LOGIC;
      I1                             :	in    STD_LOGIC;
      I0                             :	in    STD_LOGIC);
end component;


----- Component OR5 -----
component OR5
   port(
      O                              :	out   STD_LOGIC;
      I4                             :	in    STD_LOGIC;
      I3                             :	in    STD_LOGIC;
      I2                             :	in    STD_LOGIC;
      I1                             :	in    STD_LOGIC;
      I0                             :	in    STD_LOGIC);
end component;

----- Component OSC -----
component OSC
   port(
	O 			     : out STD_LOGIC
       );
end component;
attribute synthesis_noprune of OSC : component is true;

component GXTL
   port(
        O			     : out STD_LOGIC