ddr_bi_dir_instanciate.vhd

Xilinx Ise 官方源代码盘 第四章

-------------------------------------------------------------------------------
--                         Double Data Rate (DDR)                            --
--            Bi-directionnal DDR instanciation using Synplify               --
-------------------------------------------------------------------------------
--
-- GENERAL:
-- Synplify (with attribute specification) can infer Virtex-II input 
--   DDR cells. For output, tristate or bi-dir DDR instanciation is required.
--
-- The DDR resources: (See Handbook and Libraries guide for more details)
--   - Input DDR: A single external signal drives two registers in the IOB.
--       One register is clocked on the rising edge of the clock, the other 
--       register is clocked on the rising edge of the inverted clock signal.
--   - Output DDR: Two internal data signals drive two IOB registers. The 
--       single external output signal alternates from one register output to
--       the other at the rising edge of the clock signal and the rising edge 
--       of the inverted clock signal.
--   - Output DDR with tristate control: Same behavior as output DDR plus 2
--       tristate control registers enabling the output to go high impedance
--       synchroneously to the associated clock signal.
--   - Other Features:
--       - Possibility to associate input and output DDR to create Bi-dir DDR
--       - Synchroneous set/preset or asynchrouneous reset/clear
--
-- NOTES:
--   - Synplify infers Input DDR when DDR registers are forced to be mapped in 
--     IOB (attribute XC_PROPS set to value "IOB=TRUE")
-------------------------------------------------------------------------------
-- Example: Bi-directionnal DDR instanciation
--   write oper (rd_wr=0) : data_x_wr -> drr_inout
--   read  oper (rd_wr=1) : drr_inout -> data_x_rd (3-state disables write operations)
--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity ddr_bi_dir_instanciate is
  port ( clk       : in    std_logic;
         rd_wr     : in    std_logic;
         rst       : in    std_logic;
         set       : in    std_logic;
         ce        : in    std_logic;
         wdata_0   : in    std_logic;
         wdata_1   : in    std_logic;
         rdata_0   : out   std_logic;
         rdata_1   : out   std_logic;
         ddr_inout : inout std_logic );
end entity ddr_bi_dir_instanciate;

architecture behavioral of ddr_bi_dir_instanciate is

  component FDDRRSE
    port ( Q  : out std_logic;
           C0 : in  std_logic;
           C1 : in  std_logic;
           CE : in  std_logic;
           D0 : in  std_logic;
           D1 : in  std_logic;
           R  : in  std_logic;
           S  : in  std_logic);
  end component;

  signal ddr_input  : std_logic;
  signal rdata0     : std_logic;
  signal rdata1     : std_logic;
  signal ddr_output : std_logic;
  signal tri        : std_logic;

  -- The following attributes are necessary in order to ensure that the
  --   DDR registers are placed inside an IOB
  attribute XC_PROPS : string;
  attribute XC_PROPS of rdata0 : signal is "IOB=TRUE"; 
  attribute XC_PROPS of rdata1 : signal is "IOB=TRUE";

begin
  -- DDR input inference
  process (clk)
  begin
    if rising_edge(clk) then
       if ce = '1' then 
          rdata0 <= ddr_input;
       end if;
    end if;
    if falling_edge(clk) then
       if ce = '1' then 
          rdata1 <= ddr_input;
       end if;
    end if;
  end process;

  -- DDR output instanciation
  DDR_OUT: FDDRRSE
    port map ( Q  => ddr_output,
               D0 => wdata_0,
               D1 => wdata_1,
               C0 => clk,
               C1 => not clk,
               CE => ce,
               R  => rst,
               S  => set);
  
-- 3-State control (DDR 3-state instanciation + 3-state output buffer inference)
  -- DDR 3-state instanciation
  DDR_3STATE: FDDRRSE
    port map ( Q  => tri,
               D0 => not rd_wr,
               D1 => not rd_wr,
               C0 => clk,
               C1 => not clk,
               CE => ce,
               R  => rst,
               S  => set);
  -- 3-state output buffer inference
  process (tri, ddr_output)
  begin
    if tri = '1' then
      ddr_inout <= 'Z';
    else
      ddr_inout <= ddr_output ;
    end if;
  end process;
  ddr_input <= ddr_inout;


-- Other Code
  process (clk)
  begin
    if rising_edge (clk) then
      rdata_0 <= rdata0;
    end if;
    if falling_edge (clk) then
      rdata_1 <= rdata1;
    end if;
  end process;

end architecture behavioral;