ddr_out_instanciate.vhd

Xilinx Ise 官方源代码盘 第四章

-------------------------------------------------------------------------------
--                         Double Data Rate (DDR)                            --
--                 Output DDR instanciation using Synplify                   --
-------------------------------------------------------------------------------
--
-- GENERAL:
-- Synplify (with attribute specification) can infer Virtex-II input 
--   DDR cells. For output, tristate or bi-dir DDR instanciation is required.
--
-- The DDR resources: (See Handbook and Libraries guide for more details)
--   - Input DDR: A single external signal drives two registers in the IOB.
--       One register is clocked on the rising edge of the clock, the other 
--       register is clocked on the rising edge of the inverted clock signal.
--   - Output DDR: Two internal data signals drive two IOB registers. The 
--       single external output signal alternates from one register output to
--       the other at the rising edge of the clock signal and the rising edge 
--       of the inverted clock signal.
--   - Output DDR with tristate control: Same behavior as output DDR plus 2
--       tristate control registers enabling the output to go high impedance
--       synchroneously to the associated clock signal.
--   - Other Features:
--       - Possibility to associate input and output DDR to create Bi-dir DDR
--       - Synchroneous set/preset or asynchrouneous reset/clear
--
-- NOTES:
--   - Synplify infers Input DDR when DDR registers are forced to be mapped in 
--     IOB (attribute XC_PROPS set to value "IOB=TRUE")
-------------------------------------------------------------------------------
-- Log file message: (Cell usage section)
--     FDDRRSE         1 use
-------------------------------------------------------------------------------
-- Example: Output DDR instanciation
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity ddr_out_instanciate is
  port ( clk        : in  std_logic;
         ce         : in  std_logic;
         rst        : in  std_logic;
         set        : in  std_logic;
         data_0     : in  std_logic;
         data_1     : in  std_logic;
         ddr_output : out std_logic );
end entity ddr_out_instanciate;

architecture behavioral of ddr_out_instanciate is

  component FDDRRSE
    port ( Q  : out std_logic;
           C0 : in  std_logic;
           C1 : in  std_logic;
           CE : in  std_logic;
           D0 : in  std_logic;
           D1 : in  std_logic;
           R  : in  std_logic;
           S  : in  std_logic);
  end component;

begin
  -- DDR output instanciation
  U0: FDDRRSE
    port map ( Q  => ddr_output,
               D0 => data_0,
               D1 => data_1,
               C0 => clk,
               C1 => not clk,
               CE => ce,
               R  => rst,
               S  => set);
             
end architecture behavioral;