dcm.vhd

Xilinx Ise 官方源代码盘 第四章

-------------------------------------------------------------------------------
--                         Digital Clock Manager (DCM)                       --
--                DCM in de-skew mode inference using Synplify               --
-------------------------------------------------------------------------------
--
-- GENERAL:
--   Synplify (with attribute specification) can infer Virtex-II DCM 
--   cells for clock de-skew purposes. For more advanced features instanciation
--   is required.
--
-- The DCM resources: 
--   - Digital Clock Manager (DCM) provides the following functions:
--      - Clock Delay Locked Loop (DLL): DCM generates new system clocks
--          (internal or external to the FPGA), that are phase-aligned to the
--          input clock. (Clock De-skew)
--      - Digital Frequency Synthesizer (DFS): DCM generates a wide range of 
--          output clock frequencies, performing a flexible input clock 
--          multiplication or division. (Frequency Synthesis)
--      - Digital Phase Shifter (DPS): DCM provides both coarse and fine-grained
--          phase shifting with dynamic phase shift control, between DCM input
--          and output clocks. (Phase Shifting)
--          
-- NOTES:
--     - Synplify infers a DCM in mode Delay Locked Loop (DLL) when input clock
--          signal is tagged with attribute "xc_clockbuftype" set to "BUFGDLL".
--          (Clock De-skew)
--     - For other features instanciattion is required
-- Log file message:
--     - Resource Usage Report section (I/O primitives)
--          BUFGDLL        1 use
-------------------------------------------------------------------------------
-- Example: Clock De-skew mode DCM inference (with attribute)
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;   --signed arithmetics library


entity mult18x18 is
  generic ( A_WIDTH : integer := 16;
            B_WIDTH : integer := 16);
  port ( clk : in std_logic;
         ce  : in std_logic;
         a   : in  std_logic_vector(A_WIDTH-1 downto 0);
         b   : in  std_logic_vector(B_WIDTH-1 downto 0);
         p   : out std_logic_vector(A_WIDTH + B_WIDTH -1 downto 0)
         );
  attribute xc_clockbuftype : string;
  attribute xc_clockbuftype of clk : signal is "BUFGDLL";
  -- value: "BUFGDLL" forces mapping to BUFGDLL. During implementation that 
  --   macro will be decomposed in a Virtex-II DCM connected to the appropriate
  --   synchronization feedback buffer (BUFG)
end entity mult18x18;

architecture behavioral of mult18x18 is

-- other code
begin
  process (clk)
  begin
    if rising_edge(clk) then
       if ce = '1' then 
          p <= a * b;
       end if;
    end if;
  end process;

end architecture behavioral;