bram_single_128x8_read_first.vhd

Xilinx Ise 官方源代码盘 第四章

-------------------------------------------------------------------------------
--           Single port RAM inference using Synplify                        --
--            (BlockRAM in READ FIRST mode example)                          --
-------------------------------------------------------------------------------
--
-- GENERAL:
--   Synplify can infer a variety RAMs from HDL source code and generate single
--   or dual port RAMs using the distributed or Block RAM resources.
--
-- RAM resources: (See Virtex-II Handbook for details)
--    - Distributed RAM
--       - Single or dual port
--       - Synchronous write and synchronous or asynchronous read
--       - Positive or negative edge clock
--    - BlockRAM
--       - Single or dual port
--       - Synchronous read and write
--       - 18 kbits blocks
--       - Different modes to help manage possible read/write conflict
--
-- NOTES:
--    - Mapping RAM into Distributed RAM
--       - Synplify default
--    - Mapping RAM to BlockRAM
--       Behavioral description must be a one-to-one correspondence with
--         the following BlockRam signals:
--          - read and write clocks
--          - read and write addresses
--          - write enable
-- Log file message:
--    - Synplicity Xilinx Technology Mapper section
--        @N Recognized Xilinx Block SelectRAM+ 
--           RAM mem[7:0] (SINGLEPORT) RAM style READ_FIRST
--           en = NoName(n/a), rst = NoName(n/a), we = we(pos) clock = clk(pos)
--    - Resource Usage Report section
--        RAMB16_S36      1 use
-------------------------------------------------------------------------------
-- Example: Single port BlockRAM 128x8 in READ FIRST mode
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity single_128x8 is
  port ( di  : in std_logic_vector(7 downto 0);
         addr: in std_logic_vector(6 downto 0);
         we  : in std_logic;
         clk : in std_logic;
         do  : out std_logic_vector(7 downto 0));
end single_128x8;

architecture behavioral of single_128x8 is

  type mem_type is array (127 downto 0) of std_logic_vector (7 downto 0);

  signal mem: mem_type;

  attribute syn_ramstyle        : string;
  attribute syn_ramstyle of mem : signal is "block_ram";
  -- value: "select_ram"  forces Distributed RAM implementation (default)
  -- value: "registers"   forces Registers   RAM implementation
  -- value: "block_ram"   forces BlockRAM    RAM implementation
  -- value: "no_rw_check" forces BlockRAM    RAM implementation with no
  --                                   read/write address conflict checking  

begin 
  process (clk)
  begin
    if rising_edge(clk) then
      if we = '1' then
        mem(conv_integer(addr)) <= di;
      end if;
      do <= mem(conv_integer(addr));
    end if;
  end process;
end behavioral;