mult_and.vhd

Xilinx Ise 官方源代码盘 第四章

-------------------------------------------------------------------------------
--          Virtex-II MULT_AND cell inference using Synplify                 --
-------------------------------------------------------------------------------
--
-- GENERAL:
--   Synplify automatically infers Virtex-II MULT_AND cells for certain 
--     arithmetics behavioral descriptions.
--
-- MULT_AND resources: (See Virtex-II Handbook for more details)
--     - One MULT_AND gate is associate with each LUT and drives an input to 
--       the carry chain, speeding up implementation of multipliers and other
--       arithmetics operations.
--
-- STATUS:
--     - Synplify automaticaly infers MULT_AND cells for distributed 
--       multipliers descriptions
--     - Other arithmetic functions that could take advantage of the MULT_AND
--       will be implemented in the future (target release 7.1)
-------------------------------------------------------------------------------
-- Example: Signed 16 x 16 multiplier with registered outputs
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;   --signed arithmetics library
--use ieee.std_logic_unsigned.all; --unsigned arithmetics library

entity mult18x18s is
  generic ( A_WIDTH : integer := 16;
            B_WIDTH : integer := 16);
  port ( clk : in std_logic;
         ce  : in std_logic;
         a   : in  std_logic_vector(A_WIDTH-1 downto 0);
         b   : in  std_logic_vector(B_WIDTH-1 downto 0);
         p   : out std_logic_vector(A_WIDTH + B_WIDTH -1 downto 0)
         );
end entity mult18x18s;

architecture behavioral of mult18x18s is

  signal p_temp : std_logic_vector(p'range);

  attribute syn_multstyle : string;
  attribute syn_multstyle of p_temp : signal is "logic";
  -- value: "block_mult" force MULT18X18 Virtex-II block multipliers (default)
  -- value: "logic"      disable multiplier mapping to MULT18X18 cells

begin
  process (clk)
  begin
    if rising_edge(clk) then
       if ce = '1' then 
         p <= p_temp;
       end if;
    end if;
  end process;

  p_temp <= a * b;

end architecture behavioral;