dcm_freq_synth.vhd

Xilinx Ise 官方源代码盘 第四章

-------------------------------------------------------------------------------
--                       Digital Clock Manager (DCM)                         --
--        DCM in Frequency Synthesis mode instanciation using Synplify       --
-------------------------------------------------------------------------------
--
-- GENERAL:
-- Synplify (with attribute specification) can infer Virtex-II DCM 
--   cells for clock de-skew purposes. For more advanced features instanciation
--   is required.
--
-- DCM resources: 
--   - Digital Clock Manager (DCM) provides the following functions:
--      - Clock Delay Locked Loop (DLL): DCM generates new system clocks
--          (internal or external to the FPGA), that are phase-aligned to the
--          input clock. (Clock De-skew)
--      - Digital Frequency Synthesizer (DFS): DCM generates a wide range of 
--          output clock frequencies, performing a flexible input clock 
--          multiplication or division. (Frequency Synthesis)
--      - Digital Phase Shifter (DPS): DCM provides both coarse and fine-grained
--          phase shifting with dynamic phase shift control, between DCM input
--          and output clocks. (Phase Shifting)
--          
-- NOTES:
--     - Synplify infers a DCM in mode Delay Locked Loop (DLL) when input clock
--          signal is tagged with attribute "xc_clockbuftype" set to "BUFGDLL".
--          (Clock De-skew)
--     - For other features instanciattion is required
-- Log file message:
--     - Resource Usage Report section (Cell usage)
--          DCM             1 use
-------------------------------------------------------------------------------
-- Example: Frequency Synthesis mode DCM instanciation (clk=4.5 times clk_board)
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;   --signed arithmetics library

entity dcm_freq_synth is
  port ( clk33_board : in  std_logic;
         rst_dll     : in  std_logic;
         ce          : in  std_logic;
         a           : in  std_logic_vector(15 downto 0);
         b           : in  std_logic_vector(15 downto 0);
         p           : out std_logic_vector(31 downto 0);
         s           : out std_logic_vector(16 downto 0);
         locked      : out std_logic );
end entity dcm_freq_synth;

architecture structural of dcm_freq_synth is
  signal clk33_ibufg, clk0_dcm, clk0_bufg : std_logic;
  signal clkfx_dcm, clkfx180_dcm          : std_logic;
  signal clk, clk180                      : std_logic;

  component IBUFG
    port ( I : in  std_logic;
           O : out std_logic
           );
  end component;

  component BUFG
    port ( I : in  std_logic;
           O : out std_logic
           );
  end component;

  attribute DLL_FREQUENCY_MODE : string;
  attribute DFS_FREQUENCY_MODE : string;
  attribute CLKFX_MULTIPLY     : integer;
  attribute CLKFX_DIVIDE       : integer;
  attribute CLKIN_PERIOD       : string;
  attribute STARTUP_WAIT       : string;

  attribute DLL_FREQUENCY_MODE of my_dcm: label is "LOW";  -- Frequency mode selection
  attribute DFS_FREQUENCY_MODE of my_dcm: label is "HIGH"; -- Frequency Synthesis mode activation
  attribute CLKFX_MULTIPLY     of my_dcm: label is 9;      -- M=9 (acceptable range is 2-32)
  attribute CLKFX_DIVIDE       of my_dcm: label is 2;      -- D=2 (acceptable range is 1-32)
  attribute CLKIN_PERIOD       of my_dcm: label is "30.000"; -- CLKIN = 33.33MHz
  attribute STARTUP_WAIT       of my_dcm: label is "TRUE";

  component DCM
    port ( CLKIN    : in  std_logic;
           CLKFB    : in  std_logic;
           DSSEN    : in  std_logic;
           PSINCDEC : in  std_logic;
           PSEN     : in  std_logic;
           PSCLK    : in  std_logic;
           RST      : in  std_logic;
           CLK0     : out std_logic;
           CLK90    : out std_logic;
           CLK180   : out std_logic;
           CLK270   : out std_logic;
           CLK2X    : out std_logic;
           CLK2X180 : out std_logic;
           CLKDV    : out std_logic;
           CLKFX    : out std_logic;
           CLKFX180 : out std_logic;
           LOCKED   : out std_logic;
           PSDONE   : out std_logic;
           STATUS   : out std_logic_vector(7 downto 0) );
  end component;

begin

  clk_pad_ibufg : IBUFG
    port map ( I => clk33_board,
               O => clk33_ibufg );

  my_dcm: DCM
    port map ( CLKIN    => clk33_ibufg,
               CLKFB    => clk0_bufg,
               DSSEN    => '0',
               PSINCDEC => '0',
               PSEN     => '0',
               PSCLK    => '0',
               RST      => rst_dll,
               CLK0     => clk0_dcm,
               CLK90    => open,
               CLK180   => open,
               CLK270   => open,
               CLK2X    => open,
               CLK2X180 => open,
               CLKDV    => open,
               CLKFX    => clkfx_dcm,    -- CLKFX = (M/D) x CLKIN = 9/2 x 33.33 = 150MHz
               CLKFX180 => clkfx180_dcm, -- CLKFX180 is CLKFX phase shifted by 180 degrees
               LOCKED   => locked,
               PSDONE   => open,
               STATUS   => open );

  dcm_feedback_buf : BUFG         -- feedback provides phase alignment between
    port map ( I => clk0_dcm,     --   DCM signals clkfx to clkin (via clk0)
               O => clk0_bufg );
  clk_design : BUFG               -- CLKFX clock distribution buffer
    port map ( I => clkfx_dcm,    -- internal FPGA global clock: "clk"
               O => clk );
  clk180_design : BUFG            -- CLKFX 180 clock distribution buffer
    port map ( I => clkfx180_dcm, -- internal FPGA global clock = clk phase degrees
               O => clk180 );     --   by 180 degrees


-- other code
  process (clk)
  begin
    if rising_edge(clk) then
       if ce = '1' then 
          p <= a * b;
       end if;
    end if;
  end process;

  process (clk180)
  begin
    if rising_edge(clk180) then
       s <=  ( a(a'high) & a ) + ( b(b'high) & b );
    end if;
  end process;

end architecture structural;