bufgmux_instanciate.vhd

来自「Xilinx Ise 官方源代码盘 第四章」· VHDL 代码 · 共 71 行

-------------------------------------------------------------------------------
--                 BUFGMUX instanciation using Synplify                      --
-------------------------------------------------------------------------------
--
-- GENERAL:
-- Synplify does not infer BUFGMUX: Instanciation is required.
--
-- The BUFGMUX resources: (See Virtex-II Handbook for more details)
--   - BUFGMUX is a multiplexed global clock buffer that can select between 2 
--     input clocks.
--
-- NOTES:
--   - Instanciation: Each input clock of the BUFGMUX that comes from an external
--      signal should specify the "xc_padtype" attribute. By default Synplify 
--      infers a BUFGP instead of a IBUFG for that clock pad signal resulting 
--      in more resource usage and a slower design. 
--      (attribute no longuer needed in release 7.1)
-------------------------------------------------------------------------------
-- Example: BUFGMUX instanciation
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;   -- Signed arithmetics library

entity bufgmux_instanciate is
  port ( clk_pad       : in  std_logic;
         clk_debug_pad : in  std_logic;
         normal_mode   : in  std_logic;
         a             : in  std_logic_vector(15 downto 0);
         b             : in  std_logic_vector(15 downto 0);
         p             : out std_logic_vector(31 downto 0) );
  attribute xc_padtype : string;  
--  attribute xc_padtype of clk_pad:       signal is "IBUFG";
--  attribute xc_padtype of clk_debug_pad: signal is "IBUFG";
  -- this attribute forces external clock pad signal to be of type IBUFG instead
  --   of BUFGP inferred by default by Synplify
end entity bufgmux_instanciate;

architecture structural of bufgmux_instanciate is

  signal clk: std_logic;

  component BUFGMUX
    port ( O  : out std_logic;
           I0 : in  std_logic;
           I1 : in  std_logic;
           S  : in  std_logic );
  end component;

begin
  U1: BUFGMUX
    port map( 
      O  => clk,
      I0 => clk_debug_pad,
      I1 => clk_pad,
      S  => normal_mode);

-- Equivalent BUFGMUX behavioral description (Not available yet for inference)
--  clk <= clk_pad when normal_mode='1' else clk_debug; -- Not available yet for inference

-- other code
  process (clk)
  begin
    if rising_edge(clk) then
      p <= a * b;
    end if;
  end process;

end structural;