rom_32x8.vhd

Xilinx Ise 官方源代码盘 第四章

-------------------------------------------------------------------------------
--                     ROM inference using Synplify                          --
--                      (Distributed ROM example)                            --
-------------------------------------------------------------------------------
--
-- GENERAL:
--   Synplify infers ROM when all assignment values are constants in a
--   "case" or "if...else" statement
--
-- Virtex-II ROM resources:
--     - Logic
--     - Distributed ROM (Primitives: ROM16X1, ROM32X1, ROM64X1, ROM128X1,
--           ROM256X1)
--     - BlockRAM (Primitives: RAMB16...)
-- Different ROMs:
--     - asynchronous (Mapped to: Logic or Distributed ROM)
--     - synchronous  (Mapped to: Logic, Distribute ROM or BlockRAM)
--          - Clock enable
--          - Reset (output buffer)
--          - Dual port (BlockRAM only - instanciation only)
--
-- NOTES:
--     - Mapping ROM into Distributed ROM (Synplify default)
--          - At least half the available addresses must be assigned a value
--     - Mapping ROM to BlockRAM will be available in Synplify 7.1
--          - either addresses or outputs of the ROM should be registered
--          - memory block should be more than 256 different addresses
-- Log file message:
--     - Synplicity Xilinx Technology Mapper section
--          @N:"file.vhd":54:4:54:7|Generating ROM romsig[7:0]
--     - Resource Usage Report section (RAM/ROM usage summary)
--          32x1 ROMs (ROM32X1): 8
-------------------------------------------------------------------------------
-- Example: Synchronous 32X8 ROM
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity rom_32x8 is
  port ( clk   : in  std_logic;
         addr  : in  std_logic_vector(4 downto 0);
         data  : out std_logic_vector(7 downto 0));
  attribute syn_romstyle : string;
  attribute syn_romstyle of data : signal is "block_ram";
  -- value: "select_rom" forces Distributed ROM implementation (default)
  -- value: "logic"      forces Logic       ROM implementation
  -- value: "block_ram"  forces BlockRAM    ROM implementation (available in 7.1)
  
end rom_32x8;

architecture behavioral of rom_32x8 is
  signal romsig : std_logic_vector(7 downto 0);
begin
  process (addr)
  begin
    case (addr) is
      when b"00000" => romsig <= X"00";
      when b"00001" => romsig <= X"01";
      when b"00010" => romsig <= X"05";
      when b"00011" => romsig <= X"0D";
      when b"00100" => romsig <= X"1B";
      when b"00101" => romsig <= X"32";
      when b"00110" => romsig <= X"4F";
      when b"00111" => romsig <= X"6F";
      when b"01000" => romsig <= X"8F";
      when b"01001" => romsig <= X"AF";
      when b"01010" => romsig <= X"CF";
      when b"01011" => romsig <= X"EE";
      when b"01100" => romsig <= X"E5";
      when b"01101" => romsig <= X"E5";
      when b"01110" => romsig <= X"E5";
      when b"01111" => romsig <= X"01";
      when b"10000" => romsig <= X"00";
      when b"10001" => romsig <= X"11";
      when b"10010" => romsig <= X"05";
      when b"10011" => romsig <= X"0D";
      when b"10100" => romsig <= X"1E";
      when b"10101" => romsig <= X"32";
      when b"10110" => romsig <= X"FF";
      when b"10111" => romsig <= X"6F";
      when b"11000" => romsig <= X"83";
      when b"11001" => romsig <= X"AF";
      when b"11010" => romsig <= X"CF";
      when b"11011" => romsig <= X"EE";
      when b"11100" => romsig <= X"E5";
      when b"11101" => romsig <= X"C5";
      when b"11110" => romsig <= X"E5";
      when b"11111" => romsig <= X"01";
      when others   => romsig <= X"00";
    end case;
  end process;

  process(clk)
  begin
    if rising_edge(clk) then
      data <= romsig;
    end if;
  end process;
end behavioral;