state_machine.vhd

Xilinx Ise 官方源代码盘 第四章

-------------------------------------------------------------------------------
--                State machine inference using Synplify                     --
-------------------------------------------------------------------------------
--
-- Synplify attributes to control state machine inference:
--   - To declare unrecognized state machines or prevent automatic opimizations
--       of a particular state machine. Set attribute "syn_state_machine" to
--     - '1': to declare a state machine
--     - '0': to prevent state machine optimizations
--   - To control state machine encoding style set attribute "syn_encoding" to
--     - "default" -> sequential encoding machines with 0 to 4 states
--                 -> onehot     encoding for machines with 5 to 24 states
--                 -> gray       encoding for machines over 24 states
--     - "sequential": to force encoding style to binary
--     - "onehot"    : to force encoding style to onehot
--     - "gray"      : to force encoding style to gray
--     - "safe"      : adds reset logic to force the state machine to a known 
--                     state if it reaches an invalid state (not implemented
--                     exactly as described in "default" branch in source code)
--
-- NOTES:
--   - Synplify does not yet support mapping of state machines into BlockRAM
-------------------------------------------------------------------------------
-- Example: 4 states, state machine with controlling attribute syntax examples
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity state_machine is
  port ( clk            : in  std_logic;
         rst            : in  std_logic;
         ce             : in  std_logic;
         cond_init_1    : in  std_logic;
         cond_1_2       : in  std_logic;
         cond_1_3       : in  std_logic;
         cond_2_3       : in  std_logic;
         cond_3_1       : in  std_logic;
         output_state_1 : out std_logic;
         output_state_2 : out std_logic;
         output_state_3 : out std_logic );
end entity state_machine;

architecture behavioral of state_machine is
  type my_state_machine is (init , state1, state2, state3);
  signal state, next_state: my_state_machine;

  attribute syn_encoding : string;
--  attribute syn_encoding of state : signal is "gray";        -- example 1
--  attribute syn_encoding of state : signal is "safe,onehot"; -- example 2

  attribute syn_state_machine : boolean;
--  attribute syn_state_machine of state : signal is false;    -- example 3

begin

  -- State vector assignment
  process (clk, rst, ce)
  begin
    if rst = '0' then
      state <= init;
    elsif rising_edge(clk) then
      if ce = '1' then
        state <= next_state;
      end if;
    else
      state <= state;
    end if;
  end process;

  -- Next state assignments:
  process (state, cond_init_1, cond_1_2, cond_1_3, cond_2_3, cond_3_1)
  begin
    case state is 
      when init   => if    cond_init_1 = '1' then next_state <= state1;
                                             else next_state <= init; end if;
      when state1 => if    cond_1_2 = '1'    then next_state <= state2;
                     elsif cond_1_3 = '1'    then next_state <= state3;
                                             else next_state <= state1; end if;
      when state2 => if    cond_2_3 = '1'    then next_state <= state3;
                                             else next_state <= state2; end if;
      when state3 => if    cond_3_1 = '1'    then next_state <= state1;
                                             else next_state <= state3; end if;
      when others => next_state <= init;
    end case;
  end process;

  -- Assignment of outputs controlled by the state machine 
  output_state_1 <= '1' when state = state1 else '0';
  output_state_2 <= '1' when state = state2 else '0';
  output_state_3 <= '1' when state = state3 else '0';

end behavioral;