sop_instanciate.vhd

Xilinx Ise 官方源代码盘 第四章

-------------------------------------------------------------------------------
--           Virtex-II ORCY cell instanciation using Synplify                --
--                         (Sum Of Product)                                  --
-------------------------------------------------------------------------------
--
-- GENERAL:
--   Synplify does not yet support Virtex-II ORCY cells or SOP chain.
--     Instanciation is required.
--
-- Virtex-II ORCY resources: (See Virtex-II Handbook for more details)
--     - ORCY gates are associated with Sum Of Product (SOP) chain and are 
--         designed to implement fast and flexible Sum Of Product functions.
--     - Typical applications are large number of input combinatorial functions
--         that can be decomposed as sum of product.
--
-- NOTES:
--     - Synplify does not yet support Virtex-II ORCY cells or SOP chain,
--         instanciation is required.
-------------------------------------------------------------------------------
-- Example: 64 bits AND function (4 times 16 bits AND gate are ORed together)
--     AND16_ORCY performs a 16 bit AND fonction plus a OR with previous result.
--     SOP is the top module generating the design structure.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

-- Performs a AND16 + ORCY
entity AND16_ORCY is
  port ( datain  : in  std_logic_vector(0 to 15);
         orcyin  : in  std_logic;
         orcyout : out std_logic);
end entity  AND16_ORCY;

architecture structural of AND16_ORCY is
  
  signal muxcyout0, muxcyout1, muxcyout2, muxcyout3 : std_logic;

  component MUXCY
    port ( O  : out std_logic;
           CI : in  std_logic;
           DI : in  std_logic;
           S  : in  std_logic );
  end component;

  component ORCY
    port ( O  : out std_logic;
           CI : in  std_logic;
           I  : in  std_logic );
  end component;

begin
  
  U0: MUXCY 
    port map (O  => muxcyout0,
              CI => '1',
              DI => '0',
              S  => datain(0) and datain(1) and datain(2) and datain(3));

  U1: MUXCY 
    port map (O  => muxcyout1,
              CI => muxcyout0,
              DI => '0',
              S  => datain(4) and datain(5) and datain(6) and datain(7));

  U2: MUXCY 
    port map (O  => muxcyout2,
              CI => muxcyout1,
              DI => '0',
              S  => datain(8) and datain(9) and datain(10) and datain(11));

  U3: MUXCY 
    port map (O  => muxcyout3,
              CI => muxcyout2,
              DI => '0',
              S  => datain(12) and datain(13) and datain(14) and datain(15));
  U4: ORCY
    port map (I  => orcyin,
              CI => muxcyout3,
              O  => orcyout);

end architecture structural;

-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity sop_instanciate is
  port ( inbus  : in std_logic_vector(0 to 63);
         result : out std_logic); 
end entity sop_instanciate;

architecture structural of sop_instanciate is

  signal orcy1, orcy2, orcy3 : std_logic;

  component AND16_ORCY
    port ( datain  : in  std_logic_vector(0 to 15);
           orcyin  : in  std_logic;
           orcyout : out std_logic );
  end component;
begin
  U0: AND16_ORCY
  port map ( datain   => inbus(0 to 15),
             orcyin   => '0',
             orcyout  => orcy1);
  U1: AND16_ORCY
  port map ( datain   => inbus(16 to 31),
             orcyin   => orcy1,
             orcyout  => orcy2);
  U2: AND16_ORCY
  port map ( datain   => inbus(32 to 47),
             orcyin   => orcy2,
             orcyout  => orcy3);
  U3: AND16_ORCY
  port map ( datain   => inbus(48 to 63),
             orcyin   => orcy3,
             orcyout  => result);
end architecture structural;