bufgce_instanciate.vhd

Xilinx Ise 官方源代码盘 第四章

-------------------------------------------------------------------------------
--                 BUFGCE instanciation using Synplify                       --
-------------------------------------------------------------------------------
--
-- GENERAL:
--   Synplify does not infer BUFGCE: Instanciation is required.
--
-- The BUFGCE resources: (See Virtex-II Handbook for more details)
--   - BUFGCE is a multiplexed global clock buffer with a single gated input.
--     Its output is constant when clock-enable is inactive. When 
--     clock-enable is active, the input is transferred to the output. 
--   - BUFGCE  : output is low  when clock-enable is inactive
--   - BUFGCE_1: output is high when clock-enable is inactive
--   - Application: reducing power and routing
--
-- NOTES:
--   - Inference scheduled for release 7.2
--   - Instanciation: If the input of the BUFGCE is an external signal than the
--      "xc_padtype" attribute is recommended. By default Synplify infers a 
--      IBUF instead of a IBUFG for that clock pad signal resulting in a slower
--      design (attribute no longuer needed in release 7.1)
-------------------------------------------------------------------------------
-- Example: BUFGCE instanciation
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;   -- Signed arithmetics library

entity bufgce_instanciate is
  port ( clk_pad : in  std_logic;
         ce      : in  std_logic;
         a       : in  std_logic_vector(15 downto 0);
         b       : in  std_logic_vector(15 downto 0);
         p       : out std_logic_vector(31 downto 0) );
  attribute xc_padtype: string;  
  attribute xc_padtype of clk_pad: signal is "IBUFG";
  -- this attribute forces external clock pad signal to be of type IBUFG instead
  --   of IBUF inferred by default by Synplify
end entity bufgce_instanciate;

architecture structural of bufgce_instanciate is

  signal clk : std_logic;
  
  component BUFGCE
    port ( O  : out std_logic;
           CE : in  std_logic;
           I  : in  std_logic );
  end component;

begin

-- BUFGCE instanciation
  U1: BUFGCE
    port map ( O  => clk,
               CE => ce,
               I  => clk_pad);

-- Equivalent BUFGCE behavioral description (Not available yet for inference)
--  clk <= clk_pad and not ce;           -- Not available yet for inference 
--  clk <= clk_pad when ce='1' else '0'; -- Not available yet for inference

-- other code
  process (clk)
  begin
    if rising_edge(clk) then
      p <= a * b;
    end if;
  end process;

end architecture structural;