ddr_in.vhd

Xilinx Ise 官方源代码盘 第四章

-------------------------------------------------------------------------------
--                         Double Data Rate (DDR)                            --
--                   Input DDR inference using Synplify                      --
-------------------------------------------------------------------------------
--
-- GENERAL:
--   Synplify (with attribute specification) can infer Virtex-II input 
--   DDR cells. For output, tristate or bi-dir DDR instanciation is required.
--
-- DDR resources: (See Handbook and Libraries guide for more details)
--   - Input DDR: A single external signal drives two registers in the IOB.
--       One register is clocked on the rising edge of the clock, the other 
--       register is clocked on the rising edge of the inverted clock signal.
--   - Output DDR: Two internal data signals drive two IOB registers. The 
--       single external output signal alternates from one register output to
--       the other at the rising edge of the clock signal and the rising edge 
--       of the inverted clock signal.
--   - Output DDR with tristate control: Same behavior as output DDR plus 2
--       tristate control registers enabling the output to go high impedance
--       synchroneously to the associated clock signal.
--   - Other Features:
--       - Possibility to associate input and output DDR to create Bi-dir DDR
--       - Synchroneous set/preset or asynchrouneous reset/clear
--
-- NOTES:
--   - Synplify infers Input DDR when DDR registers are forced to be mapped in 
--       IOB (attribute XC_PROPS set to value "IOB=TRUE")
-------------------------------------------------------------------------------
-- Example: Input DDR inference
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity ddr_in is
  port ( clk       : in  std_logic;
         ce        : in  std_logic;
         ddr_input : in  std_logic;
         other_1   : in  std_logic;
         other_2   : in  std_logic;
         res_1     : out std_logic;
         res_2     : out std_logic );
end entity ddr_in;

architecture behavioral of ddr_in is

  signal data_1, data_2 : std_logic;

-- The following attributes are necessary in order to ensure that IOB DDR registers
--  are inferred
  attribute XC_PROPS : string;
  attribute XC_PROPS of data_1 : signal is "IOB=TRUE"; 
  attribute XC_PROPS of data_2 : signal is "IOB=TRUE";

begin
-- DDR input inference
  process (clk)
  begin
    if rising_edge(clk) then
       if ce = '1' then 
          data_1 <= ddr_input;
       end if;
    end if;
    if falling_edge(clk) then
       if ce = '1' then 
          data_2 <= ddr_input;
       end if;
    end if;
  end process;

-- Other code
  res_1 <= data_1 and other_1;
  res_2 <= data_2 and other_2;

end architecture behavioral;