srl_dynamic.vhd

Xilinx Ise 官方源代码盘 第四章

-------------------------------------------------------------------------------
--               Dynamic Shift Register inference using Synplify             --
-------------------------------------------------------------------------------
--
-- GENERAL:
--   Synplify automatically infers Virtex-II Shift-Register cells from 
--     different behavioral descriptions.
--
-- Virtex-II Shift Registers implementations: (See Handbook for more details)
--   - Flip-flops
--   - LUTs 
--      - Any LUT can be configured as a 16-bit shift register. (SRL16)
--      - Shift-in operation is synchronous to a positive clock edge (SRL16)
--          or a negative clock edge (SRL16_1).
--      - Output can be static or dynamically selectable.
--      - A dedicated output allows to cascade any number of 16-bit shift 
--          registers (SRLC16).
--      - Clock enable allows for controlling shift operations. (SRL16E)
--      - To improve shift register's clock to out performance, the last stage
--          can be implemented in register.
--
-- NOTES
--   - Synplify maps to all the above mentionned cells by default as long as:
--      - The description represents a set of two or more registers that can be
--        shifted left or right.
--      - The contents of only one register can be seen at a time, based on
--        the read address.
--   - Wider shift register descriptions are automatically decomposed into
--     cascaded cells:
--      - SRL16 for static shift register
--      - SRLC16 for dynamic shift register
--
-- ATTRIBUTES:
--   - To prevent automatic inference to shift registers, set the 
--       "syn_srlstyle" attribute to "registers". 
-- Log file message:
--   - Resource Usage Report section (SRL primitives)
--       SRLC16E        16 uses
-------------------------------------------------------------------------------
-- Example: Behavioral description of 2 dimensions dynamic shift register
--          with clock enable
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity dynamic is
  generic(  BUS_WIDTH : integer := 8; -- delay line bus width
            SRL_DEPTH : integer := 32); -- max number of delays 
  port ( data_in  : in  std_logic_vector(BUS_WIDTH-1 downto 0);
         clk      : in  std_logic;
         en       : in  std_logic;
         sel      : in  std_logic_vector(4 downto 0);
         data_out : out std_logic_vector(BUS_WIDTH-1 downto 0) );
end dynamic;

architecture behavioral of dynamic is
  type   reg_bank is array(SRL_DEPTH-1 downto 0) of std_logic_vector(BUS_WIDTH-1 downto 0);
  signal lshift_reg : reg_bank;

  attribute syn_srlstyle : string;
  attribute syn_srlstyle of lshift_reg : signal is "select_srl";
  -- "select_srl"      forces shift register mapping to SRL16 primitives (default)
  -- "registers"       forces shift register mapping to registers 
  -- "noextractff_srl" forces shift register mapping to SRL16 primitives without the
  --   timing optimizing output flip-flops

begin
  process(clk, data_in)
  begin
    if rising_edge(clk) then
      if (en = '1') then
        lshift_reg <= (lshift_reg(SRL_DEPTH-2 downto 0) & data_in);
      end if;
    end if;
  end process;
  data_out <= lshift_reg(conv_integer(sel));
end behavioral;