ddr_bi_dir_instanciate.v

Xilinx Ise 官方源代码盘 第四章

/*-----------------------------------------------------------------------------
--                         Double Data Rate (DDR)                            --
--            Bi-directionnal DDR instanciation using Synplify               --
-------------------------------------------------------------------------------
--
-- GENERAL:
-- Synplify (with attribute specification) can infer Virtex-II input 
--   DDR cells. For output, tristate or bi-dir DDR instanciation is required.
--
-- The DDR resources: (See Handbook and Libraries guide for more details)
--   - Input DDR: A single external signal drives two registers in the IOB.
--       One register is clocked on the rising edge of the clock, the other 
--       register is clocked on the rising edge of the inverted clock signal.
--   - Output DDR: Two internal data signals drive two IOB registers. The 
--       single external output signal alternates from one register output to
--       the other at the rising edge of the clock signal and the rising edge 
--       of the inverted clock signal.
--   - Output DDR with tristate control: Same behavior as output DDR plus 2
--       tristate control registers enabling the output to go high impedance
--       synchroneously to the associated clock signal.
--   - Other Features:
--       - Possibility to associate input and output DDR to create Bi-dir DDR
--       - Synchroneous set/preset or asynchrouneous reset/clear
--
-- NOTES:
--   - Synplify infers Input DDR when DDR registers are forced to be mapped in 
--     IOB (attribute XC_PROPS set to value "IOB=TRUE")
-------------------------------------------------------------------------------
-- Example: Bi-directionnal DDR instanciation
--   write oper (rd_wr=0) : data_x_wr -> drr_inout
--   read  oper (rd_wr=1) : drr_inout -> data_x_rd (3-state disables write operations)
------------------------------------------------------------------------------*/

module ddr_bi_dir_instanciate (clk, rd_wr, rst, set, ce, wdata_0, wdata_1, rdata_0, rdata_1, ddr_inout);
  input  clk;
  input  rd_wr;
  input  rst;
  input  set;
  input  ce;
  input  wdata_0;
  input  wdata_1;
  output rdata_0;
  output rdata_1;
  inout  ddr_inout;

  wire ddr_input;
  wire ddr_output;
  wire to_z;
//  reg ddr_inout;
  reg  rdata_0;
  reg  rdata_1;

  // The following attributes are necessary in order to ensure that the
  //   DDR registers are placed inside an IOB
  reg rdata0 /* synthesis xc_props = "IOB=TRUE" */ ;
  reg rdata1 /* synthesis xc_props = "IOB=TRUE" */ ;

  // DDR input inference
  always @(posedge clk)
  begin
    if (ce == 1'b1)
      rdata0 <= ddr_input;
  end

  always @(negedge clk)
  begin
    if (ce == 1'b1)
      rdata1 <= ddr_input;
  end

  // DDR output instanciation
  FDDRRSE DDR_OUT
    ( .Q (ddr_output),
      .D0(wdata_0),
      .D1(wdata_1),
      .C0(clk),
      .C1(!clk),
      .CE(ce),
      .R (rst),
      .S (set) );
  
// 3-State control (DDR 3-state instanciation + 3-state output buffer inference)
  // DDR 3-state instanciation
  FDDRRSE DDR_3STATE
    ( .Q (to_z),
      .D0(!rd_wr),
      .D1(!rd_wr),
      .C0(clk),
      .C1(!clk),
      .CE(ce),
      .R (rst),
      .S (set) );
  // 3-state output buffer inference
  assign ddr_inout = to_z ? 1'bZ : ddr_output ;

  assign ddr_input = ddr_inout;


// Other Code
  always @(posedge clk)
  begin
    rdata_0 <= rdata0;
  end

  always @(negedge clk)
  begin
    rdata_1 <= rdata1;
  end


endmodule