ddr_out_instanciate.v

来自「Xilinx Ise 官方源代码盘 第四章」· Verilog 代码 · 共 57 行

/*-----------------------------------------------------------------------------
--                         Double Data Rate (DDR)                            --
--                 Output DDR instanciation using Synplify                   --
-------------------------------------------------------------------------------
--
-- GENERAL:
-- Synplify (with attribute specification) can infer Virtex-II input 
--   DDR cells. For output, tristate or bi-dir DDR instanciation is required.
--
-- The DDR resources: (See Handbook and Libraries guide for more details)
--   - Input DDR: A single external signal drives two registers in the IOB.
--       One register is clocked on the rising edge of the clock, the other 
--       register is clocked on the rising edge of the inverted clock signal.
--   - Output DDR: Two internal data signals drive two IOB registers. The 
--       single external output signal alternates from one register output to
--       the other at the rising edge of the clock signal and the rising edge 
--       of the inverted clock signal.
--   - Output DDR with tristate control: Same behavior as output DDR plus 2
--       tristate control registers enabling the output to go high impedance
--       synchroneously to the associated clock signal.
--   - Other Features:
--       - Possibility to associate input and output DDR to create Bi-dir DDR
--       - Synchroneous set/preset or asynchrouneous reset/clear
--
-- NOTES:
--   - Synplify infers Input DDR when DDR registers are forced to be mapped in 
--     IOB (attribute XC_PROPS set to value "IOB=TRUE")
-------------------------------------------------------------------------------
-- Log file message: (Cell usage section)
--     FDDRRSE         1 use
-------------------------------------------------------------------------------
-- Example: Output DDR instanciation
-----------------------------------------------------------------------------*/

module ddr_out_instanciate (clk, ce, rst, set, data_0, data_1, ddr_output);
  input  clk;
  input  ce;
  input  rst;
  input  set;
  input  data_0;
  input  data_1;
  output ddr_output;

  // DDR output instanciation
  FDDRRSE U0
    ( .Q (ddr_output),
      .D0(data_0),
      .D1(data_1),
      .C0(clk),
      .C1(!clk),
      .CE(ce),
      .R (rst),
      .S (set) );
             
endmodule