mult18x18s_instanciate.v

Xilinx Ise 官方源代码盘 第四章

/*-----------------------------------------------------------------------------
--    Virtex-II Registered Block Multiplier instanciation using Synplify     --
-------------------------------------------------------------------------------
--
-- GENERAL:
--   Synplify automatically infers Virtex-II MULT18X18 cells from behavioral 
--   multiplier descriptions.
--
-- The multiplier resources: (See Virtex-II Handbook for more details)
--     - Logic (CLB resources)
--     - Block multipliers
--          - asynchronous (Primitive: MULT18X18)
--          - synchronous  (Primitive: MULT18X18S)
--              . clock enable
--              . synchronous reset
--          - up to 17x17 unsigned multiplication per cell
--          - up to 18x18 signed multiplication per cell (two's complement)
--          - two small multipliers fit into a single cell (instanciation only)
--
-- NOTES:
--     - Mapping multipliers into MULT18X18 cells (Synplify default)
--          - signed/unsigned 3x3 and wider multiplication support
--          - wider multiplier descriptions than acceptable range by a single
--            cell are automatically decomposed into different cells.
--     - Mapping multipliers into MULT18X18S cells
--          - no support yet for registered MULT18X18S (target release 7.1)
--          - enable the global optimization switch : "Pipelining"
--          - or apply the "syn_pipeline" attribute to the set of registers 
--             on the output of the multiplier
--     - Mapping multipliers into logic
--          - no particular constraints (often slower than block multiplier
--             implementation)
-- Log file message: (Resource Usage Report section)
--          MULT18X18S      1 use
-------------------------------------------------------------------------------
-- Example: Instanciation of a registered outputs block multiplier (MULT18X18S)
-----------------------------------------------------------------------------*/

module mult18x18s_instanciate (clk, ce, a, b, p);
  input         clk;
  input         ce;
  input  [15:0] a;
  input  [15:0] b;
  output [31:0] p;

  wire   [17:0] a_extended;
  wire   [17:0] b_extended;
  wire   [35:0] p_bmult_width;
 
  // Sign extention due to cell wider than desired multiplier
  //   i.e. 16 by 16 signed multiplication, cell is 18 by 18
  assign a_extended = {a[15], a[15], a};
  assign b_extended = {b[15], b[15], b};

  MULT18X18S U0
    ( .P (p_bmult_width),
      .A (a_extended),
      .B (b_extended),
      .C (clk),
      .CE(ce),
      .R (1'b0) );

  assign p = p_bmult_width[31:0];

endmodule