dcm.v

Xilinx Ise 官方源代码盘 第四章

/*-----------------------------------------------------------------------------
--                         Digital Clock Manager (DCM)                       --
--                DCM in de-skew mode inference using Synplify               --
-------------------------------------------------------------------------------
--
-- GENERAL:
--   Synplify (with attribute specification) can infer Virtex-II DCM 
--   cells for clock de-skew purposes. For more advanced features instanciation
--   is required.
--
-- The DCM resources: 
--   - Digital Clock Manager (DCM) provides the following functions:
--      - Clock Delay Locked Loop (DLL): DCM generates new system clocks
--          (internal or external to the FPGA), that are phase-aligned to the
--          input clock. (Clock De-skew)
--      - Digital Frequency Synthesizer (DFS): DCM generates a wide range of 
--          output clock frequencies, performing a flexible input clock 
--          multiplication or division. (Frequency Synthesis)
--      - Digital Phase Shifter (DPS): DCM provides both coarse and fine-grained
--          phase shifting with dynamic phase shift control, between DCM input
--          and output clocks. (Phase Shifting)
--          
-- NOTES:
--     - Synplify infers a DCM in mode Delay Locked Loop (DLL) when input clock
--          signal is tagged with attribute "xc_clockbuftype" set to "BUFGDLL".
--          (Clock De-skew)
--     - For other features instanciattion is required
-- Log file message:
--     - Resource Usage Report section (I/O primitives)
--          BUFGDLL        1 use
-------------------------------------------------------------------------------
-- Example: Clock De-skew mode DCM inference (with attribute)
-----------------------------------------------------------------------------*/

module mult18x18 (clk, ce, a, b, p);
  input         clk /* synthesis xc_clockbuftype = "BUFGDLL" */;
  input         ce;
  input  [15:0] a;
  input  [15:0] b;
  output [31:0] p;

  reg    [31:0] p;

/* attribute xc_clockbuftype of clk with value = "BUFGDLL" forces mapping to 
     BUFGDLL. During implementation that macro will be decomposed in a 
     Virtex-II DCM connected to the appropriate synchronization feedback buffer
     (BUFG) */

// other code
 always @(posedge clk)
  begin
    if (ce == 1'b1)
      p <= a * b;
  end

endmodule