📄 ram_single_port_128x8.srr
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$ Start of Compile
#Fri May 28 14:13:23 2004
Synplicity Verilog Compiler, version Compilers 2.6.0, Build 102R, built Jan 27 2004
Copyright (C) 1994-2004, Synplicity Inc. All Rights Reserved
@I::"D:\CD\hdl_example_v2_synplify\spro_703\verilog\ram\default\ram_single_port_128x8.v"
Verilog syntax check successful!
Options changed - recompiling
Selecting top level module ram_single_port_128x8
Synthesizing module ram_single_port_128x8
@N: CL134 :"D:\CD\hdl_example_v2_synplify\spro_703\verilog\ram\default\ram_single_port_128x8.v":60:11:60:19|Found RAM mem, depth=128, width=8
@END
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
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Synplicity Xilinx Technology Mapper, version 7.3.5, Build 256R, built Mar 25 2004
Copyright (C) 1994-2004, Synplicity Inc. All Rights Reserved
Running FSM Explorer ...
Did not find any FSM for encoding selection. Exiting ...
FSM Explorer successful!
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
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Synplicity Xilinx Technology Mapper, version 7.3.5, Build 256R, built Mar 25 2004
Copyright (C) 1994-2004, Synplicity Inc. All Rights Reserved
Clock Buffers:
Inserting Clock buffer for port clk, TNM=clk
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
------------------------------------------------------------
Net buffering Report for view:work.ram_single_port_128x8(verilog):
No nets needed buffering.
@N: FX164 |The option to pack flops in the IOB has not been specified
Writing Analyst data base D:\CD\hdl_example_v2_synplify\spro_703\verilog\ram\default\synthesis\ram_single_port_128x8.srm
Writing EDIF Netlist and constraint files
Found clock ram_single_port_128x8|clk with period 1000.00ns
##### START OF TIMING REPORT #####[
# Timing Report written on Fri May 28 14:13:25 2004
#
Top view: ram_single_port_128x8
Requested Frequency: 1.0 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT196 |Clock constraints cover all FF-to-FF, FF-to-output, input-to-FF and input-to-output paths associated with a particular clock..
Performance Summary
*******************
Worst slack in design: 995.748
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
----------------------------------------------------------------------------------------------------------------------------------
ram_single_port_128x8|clk 1.0 MHz 235.2 MHz 1000.000 4.252 995.748 inferred Inferred_clkgroup_0
==================================================================================================================================
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------------------------------------------
ram_single_port_128x8|clk ram_single_port_128x8|clk | 1000.000 995.748 | No paths - | No paths - | No paths -
==============================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
Input Ports:
Port Starting User Arrival Required
Name Reference Constraint Time Time Slack
Clock
--------------------------------------------------------------------------------------------------
addr[0] ram_single_port_128x8|clk (rising) 0.000 0.000 996.549 996.549
addr[1] ram_single_port_128x8|clk (rising) 0.000 0.000 996.549 996.549
addr[2] ram_single_port_128x8|clk (rising) 0.000 0.000 996.549 996.549
addr[3] ram_single_port_128x8|clk (rising) 0.000 0.000 996.549 996.549
addr[4] ram_single_port_128x8|clk (rising) 0.000 0.000 996.702 996.702
addr[5] ram_single_port_128x8|clk (rising) 0.000 0.000 996.977 996.977
addr[6] ram_single_port_128x8|clk (rising) 0.000 0.000 997.253 997.253
clk NA NA NA NA NA
di[0] ram_single_port_128x8|clk (rising) 0.000 0.000 998.210 998.210
di[1] ram_single_port_128x8|clk (rising) 0.000 0.000 998.210 998.210
di[2] ram_single_port_128x8|clk (rising) 0.000 0.000 998.210 998.210
di[3] ram_single_port_128x8|clk (rising) 0.000 0.000 998.210 998.210
di[4] ram_single_port_128x8|clk (rising) 0.000 0.000 998.210 998.210
di[5] ram_single_port_128x8|clk (rising) 0.000 0.000 998.210 998.210
di[6] ram_single_port_128x8|clk (rising) 0.000 0.000 998.210 998.210
di[7] ram_single_port_128x8|clk (rising) 0.000 0.000 998.210 998.210
we ram_single_port_128x8|clk (rising) 0.000 0.000 997.230 997.230
==================================================================================================
Output Ports:
Port Starting User Arrival Required
Name Reference Constraint Time Time Slack
Clock
------------------------------------------------------------------------------------------------
do[0] ram_single_port_128x8|clk (rising) NA 4.252 1000.000 995.748
do[1] ram_single_port_128x8|clk (rising) NA 4.252 1000.000 995.748
do[2] ram_single_port_128x8|clk (rising) NA 4.252 1000.000 995.748
do[3] ram_single_port_128x8|clk (rising) NA 4.252 1000.000 995.748
do[4] ram_single_port_128x8|clk (rising) NA 4.252 1000.000 995.748
do[5] ram_single_port_128x8|clk (rising) NA 4.252 1000.000 995.748
do[6] ram_single_port_128x8|clk (rising) NA 4.252 1000.000 995.748
do[7] ram_single_port_128x8|clk (rising) NA 4.252 1000.000 995.748
================================================================================================
====================================
Detailed Report for Clock: ram_single_port_128x8|clk
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------------
do[0] ram_single_port_128x8|clk FDE Q do_c[0] 0.000 995.748
do[1] ram_single_port_128x8|clk FDE Q do_c[1] 0.000 995.748
do[2] ram_single_port_128x8|clk FDE Q do_c[2] 0.000 995.748
do[3] ram_single_port_128x8|clk FDE Q do_c[3] 0.000 995.748
do[4] ram_single_port_128x8|clk FDE Q do_c[4] 0.000 995.748
do[5] ram_single_port_128x8|clk FDE Q do_c[5] 0.000 995.748
do[6] ram_single_port_128x8|clk FDE Q do_c[6] 0.000 995.748
do[7] ram_single_port_128x8|clk FDE Q do_c[7] 0.000 995.748
mem.I_1 ram_single_port_128x8|clk RAM128X1S O mem[1] 2.600 996.516
mem.I_2 ram_single_port_128x8|clk RAM128X1S O mem[2] 2.600 996.516
================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------------
do[7:0] ram_single_port_128x8|clk Port do[0] do[0] 1000.000 995.748
do[7:0] ram_single_port_128x8|clk Port do[1] do[1] 1000.000 995.748
do[7:0] ram_single_port_128x8|clk Port do[2] do[2] 1000.000 995.748
do[7:0] ram_single_port_128x8|clk Port do[3] do[3] 1000.000 995.748
do[7:0] ram_single_port_128x8|clk Port do[4] do[4] 1000.000 995.748
do[7:0] ram_single_port_128x8|clk Port do[5] do[5] 1000.000 995.748
do[7:0] ram_single_port_128x8|clk Port do[6] do[6] 1000.000 995.748
do[7:0] ram_single_port_128x8|clk Port do[7] do[7] 1000.000 995.748
do[0] ram_single_port_128x8|clk FDE D mem[0] 999.467 996.516
do[1] ram_single_port_128x8|clk FDE D mem[1] 999.467 996.516
=============================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 1000.000
= Required time: 1000.000
- Propagation time: 4.252
= Slack (critical) : 995.748
Number of logic level(s): 1
Starting point: do[0] / Q
Ending point: do[7:0] / do[0]
The start point is clocked by ram_single_port_128x8|clk [rising] on pin C
The end point is clocked by ram_single_port_128x8|clk [rising]
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
------------------------------------------------------------------------------
do[0] FDE Q Out 0.000 0.000 -
do_c[0] Net - - 0.000 - 1
do_obuf[0] OBUF I In - 0.000 -
do_obuf[0] OBUF O Out 4.252 4.252 -
do[0] Net - - 0.000 - 0
do[7:0] Port do[0] Out - 4.252 -
==============================================================================
Total path delay (propagation time + setup) of 4.252 is 4.252(100.0%) logic and 0.000(0.0%) route.
##### END OF TIMING REPORT #####]
---------------------------------------
Resource Usage Report for ram_single_port_128x8
Mapping to part: xc2v40cs144-5
Cell usage:
FDE 8 uses
RAM128X1S 8 uses
I/O primitives: 24
IBUF 16 uses
OBUF 8 uses
BUFGP 1 use
I/O Register bits: 8
Register bits not including I/Os: 0 (0%)
RAM/ROM usage summary
Single Port Rams (RAM128X1S): 8
Global Clock Buffers: 1 of 16 (6%)
Mapping Summary:
Total LUTs: 64 (12%)
Mapper successful!
Process took 0h:0m:1s realtime, 0h:0m:1s cputime
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