ram_single_port_128x8.srd

Xilinx Ise 官方源代码盘 第四章

f "noname"; #file 0
f "d:\cd\hdl_example_v2_synplify\spro_703\verilog\ram\default\ram_single_port_128x8.v"; #file 1
VNAME 'work.ram_single_port_128x8.verilog'; # view id 0
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