traplog.tlg

Xilinx Ise 官方源代码盘 第四章

Synthesizing work.top.gen
Synthesizing work.ram_rw.select_ram
Synthesizing virtex2.ram128x1s.syn_black_box
Post processing for virtex2.ram128x1s.syn_black_box
Post processing for work.ram_rw.select_ram
@W: CL159 :"syng0a00480":32:8:32:11|Input oclk is unused
Post processing for work.top.gen