dcm_freq_synth.v

Xilinx Ise 官方源代码盘 第四章

/*-----------------------------------------------------------------------------
--                       Digital Clock Manager (DCM)                         --
--        DCM in Frequency Synthesis mode instanciation using Synplify       --
-------------------------------------------------------------------------------
--
-- GENERAL:
-- Synplify (with attribute specification) can infer Virtex-II DCM 
--   cells for clock de-skew purposes. For more advanced features instanciation
--   is required.
--
-- DCM resources: 
--   - Digital Clock Manager (DCM) provides the following functions:
--      - Clock Delay Locked Loop (DLL): DCM generates new system clocks
--          (internal or external to the FPGA), that are phase-aligned to the
--          input clock. (Clock De-skew)
--      - Digital Frequency Synthesizer (DFS): DCM generates a wide range of 
--          output clock frequencies, performing a flexible input clock 
--          multiplication or division. (Frequency Synthesis)
--      - Digital Phase Shifter (DPS): DCM provides both coarse and fine-grained
--          phase shifting with dynamic phase shift control, between DCM input
--          and output clocks. (Phase Shifting)
--          
-- NOTES:
--     - Synplify infers a DCM in mode Delay Locked Loop (DLL) when input clock
--          signal is tagged with attribute "xc_clockbuftype" set to "BUFGDLL".
--          (Clock De-skew)
--     - For other features instanciattion is required
-- Log file message:
--     - Resource Usage Report section (Cell usage)
--          DCM             1 use
-------------------------------------------------------------------------------
-- Example: Frequency Synthesis mode DCM instanciation (clk=4.5 times clk_board)
-----------------------------------------------------------------------------*/

module dcm_freq_synth (clk33_board, rst_dll, ce, a, b, p, s, locked);
  input         clk33_board;
  input         rst_dll;
  input         ce;
  input  [15:0] a;
  input  [15:0] b;
  output [31:0] p;
  output [16:0] s;
  output        locked;

  reg    [31:0] p;
  reg    [16:0] s;
  wire          clk33_ibufg;
  wire          clk0_dcm;
  wire          clk0_bufg;
  wire          clkfx_dcm;
  wire          clkfx180_dcm;
  wire          clk;
  wire          clk180;

  IBUFG clk_pad_ibufg
    ( .I(clk33_board),
      .O(clk33_ibufg) );

  DCM my_dcm
    ( .CLKIN(clk33_ibufg),
      .CLKFB(clk0_bufg),
      .DSSEN(1'b0),
      .PSINCDEC(1'b0),
      .PSEN(1'b0),
      .PSCLK(1'b0),
      .RST(rst_dll),
      .CLK0(clk0_dcm),
      .CLK90(), 
      .CLK180(), 
      .CLK270(), 
      .CLK2X(), 
      .CLK2X180(), 
      .CLKDV(), 
      .CLKFX(clkfx_dcm),       // CLKFX = (M/D) x CLKIN = 9/2 x 33.33 = 150MHz
      .CLKFX180(clkfx180_dcm), // CLKFX180 is CLKFX phase shifted by 180 degrees
      .LOCKED(locked),
      .PSDONE(), 
      .STATUS() )
      /* synthesis xc_props = "DLL_FREQUENCY_MODE=LOW, DFS_FREQUENCY_MODE=LOW, CLKFX_MULTIPLY=9, CLKFX_DIVIDE=2, STARTUP_WAIT=TRUE, CLKIN_PERIOD = 30.000" */;
      // Note: Don't insert any carriage return between the attributes above.

  BUFG dcm_feedback_buf        // feedback provides phase alignment between
    ( .I(clk0_dcm),            //   DCM signals clkfx to clkin (via clk0)
      .O(clk0_bufg) );

  BUFG clk_design              // CLKFX clock distribution buffer
    ( .I(clkfx_dcm),           //   internal FPGA global clock: "clk"
      .O(clk) );

  BUFG clk180_design           // CLKFX 180 clock distribution buffer
    ( .I(clkfx180_dcm),        //   internal FPGA global clock = clk phase degrees
      .O(clk180) );            //   by 180 degrees


// other code
 always @(posedge clk)
  begin
    if (ce == 1'b1)
      p <= a * b;
  end

 always @(posedge clk180)
  begin
     s <= {a[15],a} + {b[15],b};
  end

endmodule