rom_32x8.v

Xilinx Ise 官方源代码盘 第四章

/*-----------------------------------------------------------------------------
--                     ROM inference using Synplify                          --
--                      (Distributed ROM example)                            --
-------------------------------------------------------------------------------
--
-- GENERAL:
--   Synplify infers ROM when all assignment values are constants in a
--   "case" or "if...else" statement
--
-- Virtex-II ROM resources:
--     - Logic
--     - Distributed ROM (Primitives: ROM16X1, ROM32X1, ROM64X1, ROM128X1,
--           ROM256X1)
--     - BlockRAM (Primitives: RAMB16...)
-- Different ROMs:
--     - asynchronous (Mapped to: Logic or Distributed ROM)
--     - synchronous  (Mapped to: Logic, Distribute ROM or BlockRAM)
--          - Clock enable
--          - Reset (output buffer)
--          - Dual port (BlockRAM only - instanciation only)
--
-- NOTES:
--     - Mapping ROM into Distributed ROM (Synplify default)
--          - At least half the available addresses must be assigned a value
--     - Mapping ROM to BlockRAM will be available in Synplify 7.1
--          - either addresses or outputs of the ROM should be registered
--          - memory block should be more than 256 different addresses
-- Log file message:
--     - Synplicity Xilinx Technology Mapper section
--          @N:"file.vhd":54:4:54:7|Generating ROM romsig[7:0]
--     - Resource Usage Report section (RAM/ROM usage summary)
--          32x1 ROMs (ROM32X1): 8
-------------------------------------------------------------------------------
-- Example: Synchronous 32X8 ROM
-----------------------------------------------------------------------------*/

module rom_32x8 (clk, addr, data);
  input        clk;
  input  [4:0] addr;
  output [7:0] data;

  reg [7:0] data;
  reg [7:0] romsig  /* synthesis syn_romstyle = "select_rom" */ ;
  // value: "select_rom" forces Distributed ROM implementation (default)
  // value: "logic"      forces Logic       ROM implementation
  // value: "block_ram"  forces BlockRAM    ROM implementation (available in version 7.1)

  always @(addr) 
  begin 
    case (addr)
      5'b00000: romsig = 8'h00;
      5'b00001: romsig = 8'h01;
      5'b00010: romsig = 8'h05;
      5'b00011: romsig = 8'h0D;
      5'b00100: romsig = 8'h1B;
      5'b00101: romsig = 8'h32;
      5'b00110: romsig = 8'h4F;
      5'b00111: romsig = 8'h6F;
      5'b01000: romsig = 8'h8F;
      5'b01001: romsig = 8'hAF;
      5'b01010: romsig = 8'hCF;
      5'b01011: romsig = 8'hEE;
      5'b01100: romsig = 8'hE5;
      5'b01101: romsig = 8'hE5;
      5'b01110: romsig = 8'hE5;
      5'b01111: romsig = 8'h01;
      5'b10000: romsig = 8'h00;
      5'b10001: romsig = 8'h11;
      5'b10010: romsig = 8'h05;
      5'b10011: romsig = 8'h0D;
      5'b10100: romsig = 8'h1E;
      5'b10101: romsig = 8'h32;
      5'b10110: romsig = 8'hFF;
      5'b10111: romsig = 8'h6F;
      5'b11000: romsig = 8'h83;
      5'b11001: romsig = 8'hAF;
      5'b11010: romsig = 8'hCF;
      5'b11011: romsig = 8'hEE;
      5'b11100: romsig = 8'hE5;
      5'b11101: romsig = 8'hC5;
      5'b11110: romsig = 8'hE5;
      5'b11111: romsig = 8'h01;
      default:  romsig = 8'h00;
    endcase
  end

  always @(posedge clk)
    data <= romsig;

endmodule