state_machine.v

Xilinx Ise 官方源代码盘 第四章

/*-----------------------------------------------------------------------------
--                State machine inference using Synplify                     --
-------------------------------------------------------------------------------
--
-- Synplify attributes to control state machine inference:
--   - To declare unrecognized state machines or prevent automatic opimizations
--       of a particular state machine. Set attribute "syn_state_machine" to
--     - '1': to declare a state machine
--     - '0': to prevent state machine optimizations
--   - To control state machine encoding style set attribute "syn_encoding" to
--     - "default" -> sequential encoding machines with 0 to 4 states
--                 -> onehot     encoding for machines with 5 to 24 states
--                 -> gray       encoding for machines over 24 states
--     - "sequential": to force encoding style to binary
--     - "onehot"    : to force encoding style to onehot
--     - "gray"      : to force encoding style to gray
--     - "safe"      : adds reset logic to force the state machine to a known 
--                     state if it reaches an invalid state (not implemented
--                     exactly as described in "default" branch in source code)
--
-- NOTES:
--   - Synplify does not yet support mapping of state machines into BlockRAM
-------------------------------------------------------------------------------
-- Example: 4 states, state machine with controlling attribute syntax examples
-----------------------------------------------------------------------------*/

module state_machine ( clk, rst, ce, cond_init_1, cond_1_2, cond_1_3, cond_2_3, cond_3_1, output_state_1, output_state_2, output_state_3);
  input  clk;
  input  rst;
  input  ce;
  input  cond_init_1;
  input  cond_1_2;
  input  cond_1_3;
  input  cond_2_3;
  input  cond_3_1;
  output output_state_1;
  output output_state_2;
  output output_state_3;

  reg [0:1] next_state;
  reg [0:1] state /* synthesis syn_encoding = "gray" */;     // example 1 
                            // syn_encoding = "safe,onehot"  // example 2 
                            // syn_state_machine = "false"   // example 3

  parameter init   = 2'b00;
  parameter state1 = 2'b01;
  parameter state2 = 2'b10;
  parameter state3 = 2'b11;

  // State vector assignment
  always @(posedge clk) begin
    if (rst == 1'b0)
      state <= init;
    else if (ce == 1'b1)
      state <= next_state;
    else
      state <= state;
  end

  // Next state assignments:
  always @(state or cond_init_1 or cond_1_2 or cond_1_3 or cond_2_3 or cond_3_1) begin
    case (state) 
      init  : if      (cond_init_1 == 1'b1) next_state = state1;
              else                          next_state = init;

      state1: if      (cond_1_2 == 1'b1)    next_state = state2;
              else if (cond_1_3 == 1'b1)    next_state = state3;
              else                          next_state = state1;

      state2: if      (cond_2_3 == 1'b1)    next_state = state3;
              else                          next_state = state2;

      state3: if      (cond_3_1 == 1'b1)    next_state = state1;
              else                          next_state = state3;

      default:                              next_state = init;
    endcase
  end

  // Assignment of state machine controlled outputs
  assign output_state_1 = state == state1 ? 1'b1 : 1'b0;
  assign output_state_2 = state == state2 ? 1'b1 : 1'b0;
  assign output_state_3 = state == state3 ? 1'b1 : 1'b0;

endmodule