ddr_in.v

Xilinx Ise 官方源代码盘 第四章

/*-----------------------------------------------------------------------------
--                         Double Data Rate (DDR)                            --
--                   Input DDR inference using Synplify                      --
-------------------------------------------------------------------------------
--
-- GENERAL:
--   Synplify (with attribute specification) can infer Virtex-II input 
--   DDR cells. For output, tristate or bi-dir DDR instanciation is required.
--
-- DDR resources: (See Handbook and Libraries guide for more details)
--   - Input DDR: A single external signal drives two registers in the IOB.
--       One register is clocked on the rising edge of the clock, the other 
--       register is clocked on the rising edge of the inverted clock signal.
--   - Output DDR: Two internal data signals drive two IOB registers. The 
--       single external output signal alternates from one register output to
--       the other at the rising edge of the clock signal and the rising edge 
--       of the inverted clock signal.
--   - Output DDR with tristate control: Same behavior as output DDR plus 2
--       tristate control registers enabling the output to go high impedance
--       synchroneously to the associated clock signal.
--   - Other Features:
--       - Possibility to associate input and output DDR to create Bi-dir DDR
--       - Synchroneous set/preset or asynchrouneous reset/clear
--
-- NOTES:
--   - Synplify infers Input DDR when DDR registers are forced to be mapped in 
--       IOB (attribute XC_PROPS set to value "IOB=TRUE")
-------------------------------------------------------------------------------
-- Example: Input DDR inference
-----------------------------------------------------------------------------*/

module ddr_in ( clk, ce, ddr_input, other_1, other_2, res_1, res_2);

  input  clk;
  input  ce;
  input  ddr_input;
  input  other_1;
  input  other_2;
  output res_1;
  output res_2;

// The following attributes are necessary in order to ensure that IOB DDR registers  
//  are inferred
  reg data_1 /* synthesis xc_props = "IOB=TRUE" */ ;
  reg data_2 /* synthesis xc_props = "IOB=TRUE" */ ;

// DDR input inference
  always @(posedge clk)
  begin
    if (ce == 1'b1)
      data_1 <= ddr_input;
  end
  
  always @(negedge clk)
  begin
    if (ce == 1'b1)
      data_2 <= ddr_input;
  end

// Other code
  assign res_1 = data_1 & other_1;
  assign res_2 = data_2 & other_2;

endmodule