alu.prj

Xinx ISE 官方源代码盘第二章

#
##-- Synplicity, Inc.
##-- Synplify version 7.1
##-- Project file alu.prj.
##-- Generated using ISE.

#implementation: alu
impl -add "alu"

##device options
proc findmatch {spec args} {  set idx [lsearch -glob $args $spec];  if {$idx != -1} {  return [lindex $args $idx];  } else {  return $spec;  }  }
	
proc findpackage {spec} { findmatch $spec [partdata -package [part]]}
proc findgrade   {spec} { findmatch $spec [partdata -grade   [part]]}
set_option -technology VIRTEX-E
set_option -part xcv50e
set_option -package [findpackage {cs144}]
set_option -speed_grade [findgrade {-6}]

## Libraries


## Source files
add_file -Verilog  {ALU.V}

## Additional compile options
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1
set_option -top_module alu
set_option -use_fsm_explorer 1

## Additional map options
set_option -frequency 0
set_option -fanout_limit 100
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -modular 0
set_option -retiming 0

## Additional simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

## Additional placeAndRoute options
set_option -write_apr_constraint 1

##--Set result format/file last
project -result_file {j:/project_navigator_demo/alu_vlog/alu.edn}

##-- Constraint file
add_file -constraint {j:/project_navigator_demo/alu_vlog/alu.sdc}