counter.npl

Xinx ISE 官方源代码盘第二章

JDF G
// Created by Project Navigator ver 1.0
PROJECT counter
DESIGN counter
DEVFAM virtexe
DEVFAMTIME 0
DEVICE xcv50e
DEVICETIME 0
DEVPKG cs144
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL Verilog
GENERATEDSIMULATIONMODELTIME 0
SOURCE counter.v
[Normal]
_SynthOptEffort=xstvlg, virtexe, Schematic.t_synthesize, 1036578886, High
[STATUS-ALL]
counter.ncdFile=WARNINGS,1097591191
[STRATEGY-LIST]
Normal=True