counter.dly

Xinx ISE 官方源代码盘第二章

Release 5.1i - Par F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Thu Dec 19 17:26:14 2002

File: counter.dly

 The 20 Worst Net Delays are:
-------------------------------
| Max Delay (ns)  | Netname   |
-------------------------------
   1.742            Reset_
   1.354            CntOut_3
   0.780            GLOBAL_LOGIC0
   0.739            CntOut_2
   0.636            CntOut_1
   0.534            GLOBAL_LOGIC1
   0.470            CntOut_0
   0.400            Clk
   0.000            CntOut_Madd__n0000_inst_cy_1
   0.000            Clk_0_BUFGP/IBUFG
---------------------------------

-------------------------------------------------------------------------------
                               Net Delays
-------------------------------------------------------------------------------

Clk
   Clk_0_BUFGP/BUFG.OUT
         0.400  CntOut_0.CLK
         0.400  CntOut_2.CLK

Clk_0_BUFGP/IBUFG
   Clk<0>.GCLKOUT
         0.000  Clk_0_BUFGP/BUFG.IN

CntOut_0
   CntOut_0.XQ
         0.452  CntOut<0>.O
         0.470  CntOut_0.F3

CntOut_1
   CntOut_0.YQ
         0.636  CntOut<1>.O
         0.541  CntOut_0.G3

CntOut_2
   CntOut_2.XQ
         0.734  CntOut<2>.O
         0.739  CntOut_2.F1

CntOut_3
   CntOut_2.YQ
         1.354  CntOut<3>.O
         0.545  CntOut_2.G4

CntOut_Madd__n0000_inst_cy_1
   CntOut_0.COUT
         0.000  CntOut_2.CIN

GLOBAL_LOGIC0
   PWR_GND_0.Y
         0.780  CntOut_0.G1

GLOBAL_LOGIC1
   PWR_VCC_0.X
         0.534  CntOut_0.F1

Reset_
   Reset_<0>.I
         1.682  CntOut_0.SR
         1.742  CntOut_2.SR