mode7cnt.syr

Xinx ISE 官方源代码盘第二章

Release 6.2i - xst G.30
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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--> Reading design: mode7cnt.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : mode7cnt.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : mode7cnt
Output Format                      : NGC
Target Device                      : xcv50e-8-cs144

---- Source Options
Top Module Name                    : mode7cnt
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : mode7cnt.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "fdq.vf"
Module <fdq> compiled
Compiling source file "and4or2.vf"
Module <and4or2> compiled
Compiling source file "and5or2.vf"
Module <and5or2> compiled
Compiling source file "mode7cnt.vf"
Module <mode7cnt> compiled
No errors in compilation
Analysis of file <mode7cnt.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <mode7cnt>.
Module <mode7cnt> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <mode7cnt>.
Analyzing module <fdq>.
Module <fdq> is correct for synthesis.
 
    Set user-defined property "INIT =  0" for instance <XLXI_1> in unit <fdq>.
Analyzing module <FD>.
Analyzing module <INV>.
Analyzing module <and4or2>.
Module <and4or2> is correct for synthesis.
 
Analyzing module <AND2>.
Analyzing module <OR2>.
Analyzing module <and5or2>.
Module <and5or2> is correct for synthesis.
 
Analyzing module <AND3>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <and5or2>.
    Related source file is and5or2.vf.
Unit <and5or2> synthesized.


Synthesizing Unit <and4or2>.
    Related source file is and4or2.vf.
Unit <and4or2> synthesized.


Synthesizing Unit <fdq>.
    Related source file is fdq.vf.
Unit <fdq> synthesized.


Synthesizing Unit <mode7cnt>.
    Related source file is mode7cnt.vf.
Unit <mode7cnt> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <mode7cnt> ...
Loading device for application Xst from file 'v50e.nph' in environment C:/eda/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block mode7cnt, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : mode7cnt.ngr
Top Level Output File Name         : mode7cnt
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 4

Cell Usage :
# BELS                             : 12
#      AND2                        : 5
#      AND3                        : 1
#      INV                         : 3
#      OR2                         : 3
# FlipFlops/Latches                : 3
#      FD                          : 3
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 3
#      OBUF                        : 3
=========================================================================

Device utilization summary:
---------------------------

Selected Device : v50ecs144-8 

 Number of Slices:                       2  out of    768     0%  
 Number of Slice Flip Flops:             3  out of   1536     0%  
 Number of bonded IOBs:                  3  out of     98     3%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 3     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -8

   Minimum period: 6.306ns (Maximum Frequency: 158.579MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 6.263ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               6.306ns (Levels of Logic = 3)
  Source:            XLXI_15_XLXI_1 (FF)
  Destination:       XLXI_16_XLXI_1 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: XLXI_15_XLXI_1 to XLXI_16_XLXI_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               4   0.772   1.216  XLXI_15_XLXI_1 (Q_1_OBUF)
     INV:I->O              3   0.398   1.056  XLXI_15_XLXI_2 (Q1o)
     AND2:I0->O            1   0.398   0.736  XLXI_19_XLXI_2 (XLXI_19_XLXN_8)
     OR2:I0->O             1   0.398   0.736  XLXI_19_XLXI_3 (D2)
     FD:D                      0.596          XLXI_16_XLXI_1
    ----------------------------------------
    Total                      6.306ns (2.562ns logic, 3.744ns route)
                                       (40.6% logic, 59.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset:              6.263ns (Levels of Logic = 1)
  Source:            XLXI_15_XLXI_1 (FF)
  Destination:       Q<1> (PAD)
  Source Clock:      clk rising

  Data Path: XLXI_15_XLXI_1 to Q<1>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               4   0.772   1.216  XLXI_15_XLXI_1 (Q_1_OBUF)
     OBUF:I->O                 4.275          Q_1_OBUF (Q<1>)
    ----------------------------------------
    Total                      6.263ns (5.047ns logic, 1.216ns route)
                                       (80.6% logic, 19.4% route)

=========================================================================
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Total memory usage is 55484 kilobytes