and5or2.vf

Xinx ISE 官方源代码盘第二章

// Verilog model created from and5or2.sch - Tue Oct 12 22:27:17 2004

`timescale 1ns / 1ps

module and5or2(in1, in2, in3, in4, in5, out_t);

    input in1;
    input in2;
    input in3;
    input in4;
    input in5;
   output out_t;
   
   wire XLXN_8;
   wire XLXN_9;
   
   AND2 XLXI_2 (.I0(in2), .I1(in1), .O(XLXN_9));
   OR2 XLXI_3 (.I0(XLXN_8), .I1(XLXN_9), .O(out_t));
   AND3 XLXI_4 (.I0(in5), .I1(in4), .I2(in3), .O(XLXN_8));
endmodule