mode7cnt.twr

Xinx ISE 官方源代码盘第二章

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Release 6.2i Trace G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

C:/eda/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml mode7cnt
mode7cnt.ncd -o mode7cnt.twr mode7cnt.pcf


Design file:              mode7cnt.ncd
Physical constraint file: mode7cnt.pcf
Device,speed:             xcv50e,-8 (PRODUCTION 1.69 2003-12-13)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
Q<0>        |    6.712(R)|clk_BUFGP         |   0.000|
Q<1>        |    6.451(R)|clk_BUFGP         |   0.000|
Q<2>        |    6.623(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    2.196|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Tue Oct 12 22:27:27 2004
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Peak Memory Usage: 43 MB