📄 r44b0.s
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GBLS BIG_ENDIN
BIG_ENDIN SETS "NO"
;//**********OPTIONS*******************************
;//_RAM_STARTADDRESS EQU 0xc000000
_ISR_STARTADDRESS EQU 0x0c7fff00 ;GCS6:64M DRAM/SDRAM
;//_ISR_STARTADDRESS EQU 0xc1fff00 ;GCS6:16M DRAM
;/* System */
rSYSCFG EQU 0x1c00000
;/* Cache */
rNCACHBE0 EQU 0x1c00004
rNCACHBE1 EQU 0x1c00008
;/* Bus control */
rSBUSCON EQU 0x1c40000
;/* Memory control */
rBWSCON EQU 0x1c80000
rBANKCON0 EQU 0x1c80004
rBANKCON1 EQU 0x1c80008
rBANKCON2 EQU 0x1c8000c
rBANKCON3 EQU 0x1c80010
rBANKCON4 EQU 0x1c80014
rBANKCON5 EQU 0x1c80018
rBANKCON6 EQU 0x1c8001c
rBANKCON7 EQU 0x1c80020
rREFRESH EQU 0x1c80024
rBANKSIZE EQU 0x1c80028
rMRSRB6 EQU 0x1c8002c
rMRSRB7 EQU 0x1c80030
;/* UART */
rULCON0 EQU 0x1d00000
rULCON1 EQU 0x1d04000
rUCON0 EQU 0x1d00004
rUCON1 EQU 0x1d04004
rUFCON0 EQU 0x1d00008
rUFCON1 EQU 0x1d04008
rUMCON0 EQU 0x1d0000c
rUMCON1 EQU 0x1d0400c
rUTRSTAT0 EQU 0x1d00010
rUTRSTAT1 EQU 0x1d04010
rUERSTAT0 EQU 0x1d00014
rUERSTAT1 EQU 0x1d04014
rUFSTAT0 EQU 0x1d00018
rUFSTAT1 EQU 0x1d04018
rUMSTAT0 EQU 0x1d0001c
rUMSTAT1 EQU 0x1d0401c
rUBRDIV0 EQU 0x1d00028
rUBRDIV1 EQU 0x1d04028
if BIG_ENDIN = "YES";
rUTXH0 EQU 0x1d00023
rUTXH1 EQU 0x1d04023
rURXH0 EQU 0x1d00027
rURXH1 EQU 0x1d04027
WrUTXH0 EQU 0x1d00023
WrUTXH1 EQU 0x1d04023
RdURXH0 EQU 0x1d00027
RdURXH1 EQU 0x1d04027
UTXH0 EQU (0x1d00020+3) ;//byte_access address by BDMA
UTXH1 EQU (0x1d04020+3)
URXH0 EQU (0x1d00024+3)
URXH1 EQU (0x1d04024+3)
else ; //Little Endian
rUTXH0 EQU 0x1d00020
rUTXH1 EQU 0x1d04020
rURXH0 EQU 0x1d00024
rURXH1 EQU 0x1d04024
WrUTXH0 EQU 0x1d00020
WrUTXH1 EQU 0x1d04020
;RdURXH0 EQU 0x1d00024
RdURXH1 EQU 0x1d04024
UTXH0 EQU 0x1d00020 ; //byte_access address by BDMA
UTXH1 EQU 0x1d04020
URXH0 EQU 0x1d00024
URXH1 EQU 0x1d04024
endif
;/* SIO */
rSIOCON EQU 0x1d14000
rSIODAT EQU 0x1d14004
rSBRDR EQU 0x1d14008
rIVTCNT EQU 0x1d1400c
rDCNTZ EQU 0x1d14010
;/* IIS */
rIISCON EQU 0x1d18000
rIISMOD EQU 0x1d18004
rIISPSR EQU 0x1d18008
rIISFCON EQU 0x1d1800c
if BIG_ENDIN="BIG"
rIISFIF EQU 0x1d18012
else ;//Little Endian
rIISFIF EQU 0x1d18010
endif
;/* I/O PORT */
rPCONA EQU 0x1d20000
rPDATA EQU 0x1d20004
rPCONB EQU 0x1d20008
rPDATB EQU 0x1d2000c
rPCONC EQU 0x1d20010
rPDATC EQU 0x1d20014
rPUPC EQU 0x1d20018
rPCOND EQU 0x1d2001c
rPDATD EQU 0x1d20020
rPUPD EQU 0x1d20024
rPCONE EQU 0x1d20028
rPDATE EQU 0x1d2002c
rPUPE EQU 0x1d20030
rPCONF EQU 0x1d20034
rPDATF EQU 0x1d20038
rPUPF EQU 0x1d2003c
rPCONG EQU 0x1d20040
rPDATG EQU 0x1d20044
rPUPG EQU 0x1d20048
rSPUCR EQU 0x1d2004c
rEXTINT EQU 0x1d20050
rEXTINPND EQU 0x1d20054
;/* WATCHDOG */
rWTCON EQU 0x1d30000
rWTDAT EQU 0x1d30004
rWTCNT EQU 0x1d30008
;/* ADC */
rADCCON EQU 0x1d40000
rADCPSR EQU 0x1d40004
rADCDAT EQU 0x1d40008
;/* Timer */
rTCFG0 EQU 0x1d50000
rTCFG1 EQU 0x1d50004
rTCON EQU 0x1d50008
rTCNTB0 EQU 0x1d5000c
rTCMPB0 EQU 0x1d50010
rTCNTO0 EQU 0x1d50014
rTCNTB1 EQU 0x1d50018
rTCMPB1 EQU 0x1d5001c
rTCNTO1 EQU 0x1d50020
rTCNTB2 EQU 0x1d50024
rTCMPB2 EQU 0x1d50028
rTCNTO2 EQU 0x1d5002c
rTCNTB3 EQU 0x1d50030
rTCMPB3 EQU 0x1d50034
rTCNTO3 EQU 0x1d50038
rTCNTB4 EQU 0x1d5003c
rTCMPB4 EQU 0x1d50040
rTCNTO4 EQU 0x1d50044
rTCNTB5 EQU 0x1d50048
rTCNTO5 EQU 0x1d5004c
;/* IIC */
rIICCON EQU 0x1d60000
rIICSTAT EQU 0x1d60004
rIICADD EQU 0x1d60008
rIICDS EQU 0x1d6000c
;/* RTC */
if BIG_ENDIN="YES"
rRTCCON EQU 0x1d70043
rRTCALM EQU 0x1d70053
rALMSEC EQU 0x1d70057
rALMMIN EQU 0x1d7005b
rALMHOUR EQU 0x1d7005f
rALMDAY EQU 0x1d70063
rALMMON EQU 0x1d70067
rALMYEAR EQU 0x1d7006b
rRTCRST EQU 0x1d7006f
rBCDSEC EQU 0x1d70073
rBCDMIN EQU 0x1d70077
rBCDHOUR EQU 0x1d7007b
rBCDDAY EQU 0x1d7007f
rBCDDATE EQU 0x1d70083
rBCDMON EQU 0x1d70087
rBCDYEAR EQU 0x1d7008b
rTICINT EQU 0x1d7008e
else
rRTCCON EQU 0x1d70040
rRTCALM EQU 0x1d70050
rALMSEC EQU 0x1d70054
rALMMIN EQU 0x1d70058
rALMHOUR EQU 0x1d7005c
rALMDAY EQU 0x1d70060
rALMMON EQU 0x1d70064
rALMYEAR EQU 0x1d70068
rRTCRST EQU 0x1d7006c
rBCDSEC EQU 0x1d70070
rBCDMIN EQU 0x1d70074
rBCDHOUR EQU 0x1d70078
rBCDDAY EQU 0x1d7007c
rBCDDATE EQU 0x1d70080
rBCDMON EQU 0x1d70084
rBCDYEAR EQU 0x1d70088
rTICINT EQU 0x1d7008c
endif
;/* Clock & Power management */
rPLLCON EQU 0x1d80000
rCLKCON EQU 0x1d80004
rCLKSLOW EQU 0x1d80008
rLOCKTIME EQU 0x1d8000c
;/* INTERRUPT */
rINTCON EQU 0x1e00000
rINTPND EQU 0x1e00004
rINTMOD EQU 0x1e00008
rINTMSK EQU 0x1e0000c
rI_PSLV EQU 0x1e00010
rI_PMST EQU 0x1e00014
rI_CSLV EQU 0x1e00018
rI_CMST EQU 0x1e0001c
rI_ISPR EQU 0x1e00020
rI_ISPC EQU 0x1e00024
rF_ISPR EQU 0x1e00038
rF_ISPC EQU 0x1e0003c
;/* LCD */
rLCDCON1 EQU 0x1f00000
rLCDCON2 EQU 0x1f00004
rLCDCON3 EQU 0x1f00040
rLCDSADDR1 EQU 0x1f00008
rLCDSADDR2 EQU 0x1f0000c
rLCDSADDR3 EQU 0x1f00010
rREDLUT EQU 0x1f00014
rGREENLUT EQU 0x1f00018
rBLUELUT EQU 0x1f0001c
rDP1_2 EQU 0x1f00020
rDP4_7 EQU 0x1f00024
rDP3_5 EQU 0x1f00028
rDP2_3 EQU 0x1f0002c
rDP5_7 EQU 0x1f00030
rDP3_4 EQU 0x1f00034
rDP4_5 EQU 0x1f00038
rDP6_7 EQU 0x1f0003c
rDITHMODE EQU 0x1f00044
;/* ZDMA0 */
rZDCON0 EQU 0x1e80000
rZDISRC0 EQU 0x1e80004
rZDIDES0 EQU 0x1e80008
rZDICNT0 EQU 0x1e8000c
rZDCSRC0 EQU 0x1e80010
rZDCDES0 EQU 0x1e80014
rZDCCNT0 EQU 0x1e80018
;/* ZDMA1 */
rZDCON1 EQU 0x1e80020
rZDISRC1 EQU 0x1e80024
rZDIDES1 EQU 0x1e80028
rZDICNT1 EQU 0x1e8002c
rZDCSRC1 EQU 0x1e80030
rZDCDES1 EQU 0x1e80034
rZDCCNT1 EQU 0x1e80038
;/* BDMA0 */
rBDCON0 EQU 0x1f80000
rBDISRC0 EQU 0x1f80004
rBDIDES0 EQU 0x1f80008
rBDICNT0 EQU 0x1f8000c
rBDCSRC0 EQU 0x1f80010
rBDCDES0 EQU 0x1f80014
rBDCCNT0 EQU 0x1f80018
;/* BDMA1 */
rBDCON1 EQU 0x1f80020
rBDISRC1 EQU 0x1f80024
rBDIDES1 EQU 0x1f80028
rBDICNT1 EQU 0x1f8002c
rBDCSRC1 EQU 0x1f80030
rBDCDES1 EQU 0x1f80034
rBDCCNT1 EQU 0x1f80038
;/* ISR */
pISR_RESET EQU (_ISR_STARTADDRESS+0x0)
pISR_UNDEF EQU (_ISR_STARTADDRESS+0x4)
pISR_SWI EQU (_ISR_STARTADDRESS+0x8)
pISR_PABORT EQU (_ISR_STARTADDRESS+0xc)
pISR_DABORT EQU (_ISR_STARTADDRESS+0x10)
pISR_RESERVED EQU (_ISR_STARTADDRESS+0x14)
pISR_IRQ EQU (_ISR_STARTADDRESS+0x18)
pISR_FIQ EQU (_ISR_STARTADDRESS+0x1c)
pISR_ADC EQU (_ISR_STARTADDRESS+0x20)
pISR_RTC EQU (_ISR_STARTADDRESS+0x24)
pISR_UTXD1 EQU (_ISR_STARTADDRESS+0x28)
pISR_UTXD0 EQU (_ISR_STARTADDRESS+0x2c)
pISR_SIO EQU (_ISR_STARTADDRESS+0x30)
pISR_IIC EQU (_ISR_STARTADDRESS+0x34)
pISR_URXD1 EQU (_ISR_STARTADDRESS+0x38)
pISR_URXD0 EQU (_ISR_STARTADDRESS+0x3c)
pISR_TIMER5 EQU (_ISR_STARTADDRESS+0x40)
pISR_TIMER4 EQU (_ISR_STARTADDRESS+0x44)
pISR_TIMER3 EQU (_ISR_STARTADDRESS+0x48)
pISR_TIMER2 EQU (_ISR_STARTADDRESS+0x4c)
pISR_TIMER1 EQU (_ISR_STARTADDRESS+0x50)
pISR_TIMER0 EQU (_ISR_STARTADDRESS+0x54)
pISR_UERR01 EQU (_ISR_STARTADDRESS+0x58)
pISR_WDT EQU (_ISR_STARTADDRESS+0x5c)
pISR_BDMA1 EQU (_ISR_STARTADDRESS+0x60)
pISR_BDMA0 EQU (_ISR_STARTADDRESS+0x64)
pISR_ZDMA1 EQU (_ISR_STARTADDRESS+0x68)
pISR_ZDMA0 EQU (_ISR_STARTADDRESS+0x6c)
pISR_TICK EQU (_ISR_STARTADDRESS+0x70)
pISR_EINT4567 EQU (_ISR_STARTADDRESS+0x74)
pISR_EINT3 EQU (_ISR_STARTADDRESS+0x78)
pISR_EINT2 EQU (_ISR_STARTADDRESS+0x7c)
pISR_EINT1 EQU (_ISR_STARTADDRESS+0x80)
pISR_EINT0 EQU (_ISR_STARTADDRESS+0x84)
;/* PENDING BIT */
;//CAUTION:You must clear the pending bit as general special register.
;// it's different way with KS32C6x00
BIT_ADC EQU (0x1)
BIT_RTC EQU (0x1<<1)
BIT_UTXD1 EQU (0x1<<2)
BIT_UTXD0 EQU (0x1<<3)
BIT_SIO EQU (0x1<<4)
BIT_IIC EQU (0x1<<5)
BIT_URXD1 EQU (0x1<<6)
BIT_URXD0 EQU (0x1<<7)
BIT_TIMER5 EQU (0x1<<8)
BIT_TIMER4 EQU (0x1<<9)
BIT_TIMER3 EQU (0x1<<10)
BIT_TIMER2 EQU (0x1<<11)
BIT_TIMER1 EQU (0x1<<12)
BIT_TIMER0 EQU (0x1<<13)
BIT_UERR01 EQU (0x1<<14)
BIT_WDT EQU (0x1<<15)
BIT_BDMA1 EQU (0x1<<16)
BIT_BDMA0 EQU (0x1<<17)
BIT_ZDMA1 EQU (0x1<<18)
BIT_ZDMA0 EQU (0x1<<19)
BIT_TICK EQU (0x1<<20)
BIT_EINT4567 EQU (0x1<<21)
BIT_EINT3 EQU (0x1<<22)
BIT_EINT2 EQU (0x1<<23)
BIT_EINT1 EQU (0x1<<24)
BIT_EINT0 EQU (0x1<<25)
BIT_GLOBAL EQU (0x1<<26)
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