mcf5206.h

coldfire5206芯片平台的升级程序

#ifndef  MCF5206_H
  #define MCF5206_H

/**
 *  a interface that provide MCF5206's registers address, intrrupt vector
 *  assignment, etc
 *
 *  @author   lilinghua
 *  @version  1.0
 */
class MCF5206
{
public:

   // register address define
   enum Regs
   {
			MBAR  = 0x60000000,    // memory base address


      // ICR1 to ICR13 are Interrupt control register ( 8 bit, read/write)
			ICR1  = MBAR + 0x14,   // External IRQ1/IPL1
      ICR2  = MBAR + 0x15,   // External IPL2
      ICR3  = MBAR + 0x16,   // External IPL3
      ICR4  = MBAR + 0x17,   // External IRQ4/IPL4
      ICR5  = MBAR + 0x18,   // External IPL5
      ICR6  = MBAR + 0x19,   // External IPL6
      ICR7  = MBAR + 0x1a,   // External IRQ7/IPL7
      ICR8  = MBAR + 0x1b,   // SWT
      ICR9  = MBAR + 0x1c,   // Timer 1 interrupt
      ICR10 = MBAR + 0x1d,   // Timer 2 interrupt
      ICR11 = MBAR + 0x1e,   // MBUS Interrupt
      ICR12 = MBAR + 0x1f,   // UART 1 interrupt
			ICR13 = MBAR + 0x20,   // UART 2 interrupt

      IMR   = MBAR + 0x36,   // Interrupt mask(16 bits, read/write)
      IPR   = MBAR + 0x3a,   // Interrupt pending (16 bits, read)
      RSR   = MBAR + 0x40,   // Reset status(8 bits, read/write)
      SYPCR = MBAR + 0x41,   // System protection control(8 bits, read/write)
      SWIVR = MBAR + 0x42,   // Software wotchdog interrupt vector(8 bits,
                             // read/write)
      SWSR  = MBAR + 0x43,   // Software wotchdog service(8 bits, read/write)
      PAR   = MBAR + 0xcb,   // pin assignment(8 bits, read/write)

      TMR1  = MBAR + 0x100,  // Timer1 mode register(16 bits, read/write)
      TRR1  = MBAR + 0x104,  // Timer1 Reference register(16 bits, read/write)
	  TCN1	= MBAR + 0x10C,	 // timer1 count
      TER1  = MBAR + 0x111,  // Timer1 Reference(8 bits, read/write)

      TMR2  = MBAR + 0x120,  // Timer2 mode register(16 bits, read/write)
      TRR2  = MBAR + 0x124,  // Timer2 Reference register(16 bits, read/write)
	  TCN2	= MBAR + 0x12C,	 // timer1 count
      TER2  = MBAR + 0x131,  // Timer2 Reference(8 bits, read/write)
	 
      UART1_BASE = MBAR + 0x140, // UART1 reisters group base address
      UART2_BASE = MBAR + 0x180, // UART2 reisters group base address

      PPDDR = MBAR + 0x1c5, // Port A data direction register
      PPDAT = MBAR + 0x1c9  // Port A data register

	 };

	 // interrupt level define
	 enum INT_LEVEL
	 {
			// external interrupts
			IL_EINT1  = 0,   // no interrupt request
			IL_EINT2  = 2,   // FPGA uart0~3
			IL_EINT3  = 3,   // FPGA uart4~7
			IL_EINT4  = 4,   // net
			IL_EINT5  = 0,   // no interrupt request
			IL_EINT6  = 0,   // no interrupt request
			IL_EINT7  = 0,   // no interrupt request

			IL_SWT    = 0,   // no interrupt request
			IL_TIMER1 = 1,
			IL_TIMER2 = 6,
			IL_MBUS   = 2,   // NOTE: share the same interrupt level with EINT2  
			IL_UART1  = 5,
			IL_UART2  = 5,
      IL_UNUSED7= 7    // unused interrupt level 7
	 };

	 // interrupt vector assignment
	 enum INT_VECTOR
	 {
			AUTO_VECT_START = 24,
			USER_DEF_START  = 64,

			// external interrupts
			IV_EINT1  = AUTO_VECT_START + 1,
			IV_EINT2  = AUTO_VECT_START + 2,
			IV_EINT3  = AUTO_VECT_START + 3,
			IV_EINT4  = AUTO_VECT_START + 4,
			IV_EINT5  = AUTO_VECT_START + 5,
			IV_EINT6  = AUTO_VECT_START + 6,
			IV_EINT7  = AUTO_VECT_START + 7,

			IV_SWT    = AUTO_VECT_START + 7,  // SWT

			IV_TIMER1 = AUTO_VECT_START + IL_TIMER1,  // NUCLUES driver timer
			IV_TIMER2 = AUTO_VECT_START + IL_TIMER2,  // 
			IV_MBUS   = AUTO_VECT_START + IL_MBUS,    // MBUS
			IV_UART1  = USER_DEF_START,               // UART1
			IV_UART2  = USER_DEF_START + 1            // UART2
	 };

	 // interrupt priority define
	 enum INT_PRIORITY
	 {
			// external interrupts
			IP_EINT1  = 0,
			IP_EINT2  = 2,  // use different priority as MBUS
			IP_EINT3  = 0,
			IP_EINT4  = 0,
			IP_EINT5  = 0,
			IP_EINT6  = 0,
			IP_EINT7  = 0,

			IP_SWT    = 0,
			IP_TIMER1 = 0,
			IP_TIMER2 = 0,
			IP_MBUS   = 0,
			IP_UART1  = 2,
			IP_UART2  = 1
	 };

	 // interrupt autovect or not
	 enum INT_AUTOVECT
	 {
			IAV_YES = 0x80,   // auto-vector interrupt
			IAV_NO  = 0x00    // non auto-vector interrupt
	 };


	/**
	 * 1. Interrupt mask register bits define:
	 *    bit15 ~ bit8: unused/unused/UART1/UART2/   MBUS/ TIMER1/TIMER2/SWT
	 *    bit7  ~ bit0: EINT7/ EINT6/ EINT5/EINT4/   EINT3/EINT2/ EINT1/ unused
	 */
	 enum INT_MASK_BIT
	 {
			IM_UNUSED1= 0x0001,

			IM_EINT1  = 0x0002,
			IM_EINT2  = 0x0004,
			IM_EINT3  = 0x0008,
			IM_EINT4  = 0x0010,
			IM_EINT5  = 0x0020,
			IM_EINT6  = 0x0040,
			IM_EINT7  = 0x0080,

			IM_SWT    = 0x0100,
			IM_TIMER1 = 0x0200,
			IM_TIMER2 = 0x0400,
			IM_MBUS   = 0x0800,
			IM_UART1  = 0x1000,
			IM_UART2  = 0x2000,

			IM_UNUSED2= 0x4000,
			IM_UNUSED3= 0x8000,

			IM_ALL    = 0xffff
	 };
};


// write one byte to the given address
VOID WriteByte(UINT32,  UCHAR);

// read one byte from the given address
UCHAR ReadByte(UINT32);

// make Interrupt Control Register context from interrupt level, priority and
// autovect flag
UCHAR MakeICR(UCHAR, UCHAR, UCHAR);

// MCF5206 initialize function
VOID  MCF5206Init( VOID );

VOID  MCF5206InitInterrupts( VOID );

// functions for interrupt control
VOID EnableSysInterrupt( UINT16 );
VOID DisableSysInterrupt( UINT16 );

extern "C" VOID  SecondTimerLisr( VOID );
extern "C" VOID  DummyLisr( VOID );

VOID  Init5206Timer1( VOID );

VOID  Init5206Timer2( VOID );

VOID  ShowCpuStatus( VOID );

//VOID  EnableBacklight( VOID );

//VOID  ShutDownSystem( VOID );

void Sleep(UINT32 tmSize);

#endif