fpga.h

coldfire5206芯片平台的升级程序

#ifndef FPGA_H
   #define FPGA_H

#define FPGA_UART0_DR  0x00600040  //UART0 Data Registr
#define FPGA_UART0_CR  0x00600042  //UART0 Command/status Register
#define FPGA_UART0_BR  0x00600043  //UART0 baud rate Register(0~5: 4800,9600,19200,38400,57600,115200)

#define FPGA_UART1_DR  0x00600044  //UART1 Data Registr
#define FPGA_UART1_CR  0x00600046  //UART1 Command/status Register
#define FPGA_UART1_BR  0x00600047  //UART1 baud rate Register(0~5: 4800,9600,19200,38400,57600,115200)

#define FPGA_UART2_DR  0x00600048  //UART2 Data Registr
#define FPGA_UART2_CR  0x0060004a  //UART2 Command/status Register
#define FPGA_UART2_BR  0x0060004b  //UART2 baud rate Register(0~5: 4800,9600,19200,38400,57600,115200)

#define FPGA_UART3_DR  0x0060004c  //UART3 Data Registr
#define FPGA_UART3_CR  0x0060004e  //UART3 Command/status Register
#define FPGA_UART3_BR  0x0060004f  //UART3 baud rate Register(0~5: 4800,9600,19200,38400,57600,115200)

#define FPGA_UART4_DR  0x00600050  //UART4 Data Registr
#define FPGA_UART4_CR  0x00600052  //UART4 Command/status Register
#define FPGA_UART4_BR  0x00600053  //UART4 baud rate Register(0~5: 4800,9600,19200,38400,57600,115200)

#define FPGA_UART5_DR  0x00600054  //UART5 Data Registr
#define FPGA_UART5_CR  0x00600056  //UART5 Command/status Register
#define FPGA_UART5_BR  0x00600057  //UART5 baud rate Register(0~5: 4800,9600,19200,38400,57600,115200)

#define FPGA_UART6_DR  0x00600058  //UART6 Data Registr
#define FPGA_UART6_CR  0x0060005a  //UART6 Command/status Register
#define FPGA_UART6_BR  0x0060005b  //UART6 baud rate Register(0~5: 4800,9600,19200,38400,57600,115200)

#define FPGA_UART7_DR  0x0060005c  //UART7 Data Registr
#define FPGA_UART7_CR  0x0060005e  //UART7 Command/status Register
#define FPGA_UART7_BR  0x0060005f  //UART7 baud rate Register(0~5: 4800,9600,19200,38400,57600,115200)

#define  DAPORT       0x00600024   // D/A output port address

#define  VPORT        0x500000      //字符屏起始地址
#define  WPORT        0x540000      //波形屏起始地址
#define  FPGASTATE    0x60000174    //FPGA状态位
#define  UOP0         0x6000017C
#define  UOP1         0x60000178
#define  UOP2         0x600001BC    //FPGA /INI Status Port
#define  UOP3         0x600001B8    //FPGA /AC Control Port
#define  IOP3         0x00B0000E

#define  DISP_CONTROL_REGISTER		0x600000	  //显示控制寄存器

void InitFpga(UINT32 fpga_data_addr, UINT32 fpga_data_len = 0);


#endif