📄 netdrv.h
字号:
/*
FileName: netdrv.h
Description: hardware resource definations.
Version: v1.0
History:
<author> <time> <desc>
Ason 2001.5 establish this file
*/
/*
Address Map. 0 based
A0 A18 A17 A14 A19 A15 A13 A11 A12 A16
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
0x00 0 0 0 0 0 0 0 0 0 0 -> 0x00000
0x01 1 0 0 0 0 0 0 0 0 0 -> 0x00001
0x02 0 1 0 0 0 0 0 0 0 0 -> 0x40000
0x03 1 1 0 0 0 0 0 0 0 0 -> 0x40001
0x04 0 0 1 0 0 0 0 0 0 0 -> 0x20000
0x05 1 0 1 0 0 0 0 0 0 0 -> 0x20001
0x06 0 1 1 0 0 0 0 0 0 0 -> 0x60000
0x07 1 1 1 0 0 0 0 0 0 0 -> 0x60001
0x08 0 0 0 1 0 0 0 0 0 0 -> 0x04000
0x09 1 0 0 1 0 0 0 0 0 0 -> 0x04001
0x0a 0 1 0 1 0 0 0 0 0 0 -> 0x44000
0x0b 1 1 0 1 0 0 0 0 0 0 -> 0x44001
0x0c 0 0 1 1 0 0 0 0 0 0 -> 0x24000
0x0d 1 0 1 1 0 0 0 0 0 0 -> 0x24001
0x0e 0 1 1 1 0 0 0 0 0 0 -> 0x64000
0x0f 1 1 1 1 0 0 0 0 0 0 -> 0x64001
A0 A18 A17 A14 A19 A15 A13 A11 A12 A16
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
0x10 0 0 0 0 1 0 0 0 0 0 -> 0x80000
0x11 1 0 0 0 1 0 0 0 0 0 -> 0x80001
0x12 0 1 0 0 1 0 0 0 0 0 -> 0xc0000
0x13 1 1 0 0 1 0 0 0 0 0 -> 0xc0001
0x14 0 0 1 0 1 0 0 0 0 0 -> 0xa0000
0x15 1 0 1 0 1 0 0 0 0 0 -> 0xa0001
0x16 0 1 1 0 1 0 0 0 0 0 -> 0xe0000
0x17 1 1 1 0 1 0 0 0 0 0 -> 0xe0001
0x18 0 0 0 1 1 0 0 0 0 0 -> 0x84000
0x19 1 0 0 1 1 0 0 0 0 0 -> 0x84001
0x1a 0 1 0 1 1 0 0 0 0 0 -> 0xc4000
0x1b 1 1 0 1 1 0 0 0 0 0 -> 0xc4001
0x1c 0 0 1 1 1 0 0 0 0 0 -> 0xa4000
0x1d 1 0 1 1 1 0 0 0 0 0 -> 0xa4001
0x1e 0 1 1 1 1 0 0 0 0 0 -> 0xe4000
0x1f 1 1 1 1 1 0 0 0 0 0 -> 0xe4001
*/
/*
Address Map. 200 based
A0 A18 A17 A14 A19 A15 A13 A11 A12 A16
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
0x200 0 0 0 0 0 0 0 0 0 1 -> 0x10000
0x201 1 0 0 0 0 0 0 0 0 1 -> 0x10001
0x202 0 1 0 0 0 0 0 0 0 1 -> 0x50000
0x203 1 1 0 0 0 0 0 0 0 1 -> 0x50001
0x204 0 0 1 0 0 0 0 0 0 1 -> 0x30000
0x205 1 0 1 0 0 0 0 0 0 1 -> 0x30001
0x206 0 1 1 0 0 0 0 0 0 1 -> 0x70000
0x207 1 1 1 0 0 0 0 0 0 1 -> 0x70001
0x208 0 0 0 1 0 0 0 0 0 1 -> 0x14000
0x209 1 0 0 1 0 0 0 0 0 1 -> 0x14001
0x20a 0 1 0 1 0 0 0 0 0 1 -> 0x54000
0x20b 1 1 0 1 0 0 0 0 0 1 -> 0x54001
0x20c 0 0 1 1 0 0 0 0 0 1 -> 0x34000
0x20d 1 0 1 1 0 0 0 0 0 1 -> 0x34001
0x20e 0 1 1 1 0 0 0 0 0 1 -> 0x74000
0x20f 1 1 1 1 0 0 0 0 0 1 -> 0x74001
A0 A18 A17 A14 A19 A15 A13 A11 A12 A16
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
0x210 0 0 0 0 1 0 0 0 0 1 -> 0x90000
0x211 1 0 0 0 1 0 0 0 0 1 -> 0x90001
0x212 0 1 0 0 1 0 0 0 0 1 -> 0xd0000
0x213 1 1 0 0 1 0 0 0 0 1 -> 0xd0001
0x214 0 0 1 0 1 0 0 0 0 1 -> 0xb0000
0x215 1 0 1 0 1 0 0 0 0 1 -> 0xb0001
0x216 0 1 1 0 1 0 0 0 0 1 -> 0xf0000
0x217 1 1 1 0 1 0 0 0 0 1 -> 0xf0001
0x218 0 0 0 1 1 0 0 0 0 1 -> 0x94000
0x219 1 0 0 1 1 0 0 0 0 1 -> 0x94001
0x21a 0 1 0 1 1 0 0 0 0 1 -> 0xd4000
0x21b 1 1 0 1 1 0 0 0 0 1 -> 0xd4001
0x21c 0 0 1 1 1 0 0 0 0 1 -> 0xb4000
0x21d 1 0 1 1 1 0 0 0 0 1 -> 0xb4001
0x21e 0 1 1 1 1 0 0 0 0 1 -> 0xf4000
0x21f 1 1 1 1 1 0 0 0 0 1 -> 0xf4001
*/
// define the base address of MAC controller.
#define MACINTLEVEL 4
#define MACBASEADD 0x400000L
//#define IMR_ADDR (0x60000036)
// define the register address of page 0.
#define CRADD ( MACBASEADD + 0x10000 ) // offset 0.
#define PSTARTADD ( MACBASEADD + 0x10001 ) // offset 1.
#define PSTOPADD ( MACBASEADD + 0x50000 ) // offset 2.
#define BNRYADD ( MACBASEADD + 0x50001 ) // offset 3.
#define TSRADD ( MACBASEADD + 0x30000 ) // offset 4. read
#define TPSRADD TSRADD // offset 4. write
#define NCRADD ( MACBASEADD + 0x30001 ) // offset 5. read
#define TBCR0ADD NCRADD // offset 5. write
#define CPR1ADD ( MACBASEADD + 0x70000 ) // offset 6. read
#define TBCR1ADD CPR1ADD // offset 6. write
#define ISRADD ( MACBASEADD + 0x70001 ) // offset 7.
#define CRDA0ADD ( MACBASEADD + 0x14000 ) // offset 8. read
#define RSAR0ADD CRDA0ADD // offset 8. write
#define CRDA1ADD ( MACBASEADD + 0x14001 ) // offset 9. read
#define RSAR1ADD CRDA1ADD // offset 9. write
#define RBCR0ADD ( MACBASEADD + 0x54000 ) // offset a. write
#define RBCR1ADD ( MACBASEADD + 0x54001 ) // offset b. write
#define RSRADD ( MACBASEADD + 0x34000 ) // offset c. read
#define RCRADD RSRADD // offset c. write
#define CNTR0ADD ( MACBASEADD + 0x34001 ) // offset d. read
#define TCRADD CNTR0ADD // offset d. write
#define CNTR1ADD ( MACBASEADD + 0x74000 ) // offset e. read
#define DCRADD CNTR1ADD // offset e. write
#define CNTR2ADD ( MACBASEADD + 0x74001 ) // offset f. read
#define IMRADD CNTR2ADD // offset f. write
#define DATAPORTADD ( MACBASEADD + 0x90000 ) // offset 10,11.
#define DATAPORT1ADD ( MACBASEADD + 0x90000 ) // offset 10.
#define DATAPORT2ADD ( MACBASEADD + 0x90001 ) // offset 11.
#define IFGS1ADD ( MACBASEADD + 0xd0000 ) // offset 12.
#define IFGS2ADD ( MACBASEADD + 0xd0001 ) // offset 13.
#define MIIEEPROMADD ( MACBASEADD + 0xb0000 ) // offset 14.
#define TESTADD ( MACBASEADD + 0xb0001 ) // offset 15.
#define IFGADD ( MACBASEADD + 0xf0000 ) // offset 16.
#define GPIADD ( MACBASEADD + 0xf0001 ) // offset 17. read
#define GPOCADD GPIADD // offset 17. write
// define the register address of page 1.
#define PARA0ADD ( MACBASEADD + 0x10001 ) // offset 1. read
#define PAR0ADD PARA0ADD // offset 1. write
#define PARA1ADD ( MACBASEADD + 0x50000 ) // offset 2. read
#define PAR1ADD PARA1ADD // offset 2. write
#define PARA2ADD ( MACBASEADD + 0x50001 ) // offset 3. read
#define PAR2ADD PARA2ADD // offset 3. write
#define PARA3ADD ( MACBASEADD + 0x30000 ) // offset 4. read
#define PAR3ADD PARA3ADD // offset 4. write
#define PARA4ADD ( MACBASEADD + 0x30001 ) // offset 5. read
#define PAR4ADD PARA4ADD // offset 5. write
#define PARA5ADD ( MACBASEADD + 0x70000 ) // offset 6. read
#define PAR5ADD PARA6ADD // offset 6. write
#define CPRADD ( MACBASEADD + 0x70001 ) // offset 7.
#define MAR0ADD ( MACBASEADD + 0x14000 ) // offset 8.
#define MAR1ADD ( MACBASEADD + 0x14001 ) // offset 9.
#define MAR2ADD ( MACBASEADD + 0x54000 ) // offset a.
#define MAR3ADD ( MACBASEADD + 0x54001 ) // offset b.
#define MAR4ADD ( MACBASEADD + 0x34000 ) // offset c.
#define MAR5ADD ( MACBASEADD + 0x34001 ) // offset d.
#define MAR6ADD ( MACBASEADD + 0x74000 ) // offset e.
#define MAR7ADD ( MACBASEADD + 0x74001 ) // offset f.
// Some features used by MII access.
#define MII_MDO_BIT_POSITION 3
#define MII_MDO_MASK 8
#define MII_WRITE 0
#define MII_READ 2
#define MII_CLK 1
#define PHY_ADDR_ALIGN 23
#define REG_ADDR_ALIGN 18
#define PRE ((UINT32)(0xFFFFFFFF))
#define MII_READ_FRAME ((UINT32)(0x60000000))
#define MII_WRITE_FRAME ((UINT32)(0x50020000))
#define MII_MDI_BIT_POSITION 2
#define MII_MDI_MASK 4
#define MII_READ_DATA_MASK MII_MDI_MASK
#define MII_WRITE_TS 2
typedef struct
{
UINT32 PacketReallyReceived; // packet really received.
UINT32 PacketReallyReceivedTcpip; // TCP/IP packet really received.
UINT32 PacketReallyReceivedVBCare; // VB packet really received.
UINT32 PacketReallyReceivedVBNotCare; // VB packet discarded.
UINT32 PacketReceived; // packet received (actually, interrupts.).
UINT32 PacketReceivedWithError; // received with error, but don't know
// why, maybe following reasons.
UINT32 PacketReceivedIntact; // packet received intact.
UINT32 PacketReceviedCRCErr; // packet received with CRC error.
UINT32 PacketReceviedFAEErr; // packet received with FA error.
UINT32 PacketReceivedFIFOErr; // packet received with FIFO error.
UINT32 PacketReceivedMissErr; // packet received with miss error.
UINT32 PacketReceivedBMpTimes; // multi-broadcast packets.
UINT32 PacketReceivedDisabled; // receive disabled.
}STSTABOUTRCV;
typedef struct
{
UINT32 TransmitTimes;
UINT32 TransmitTimesWithError;
UINT32 TransmitOWCErr; // out of window collision.
UINT32 TransmitABTErr; // transmit abort because of collision.
UINT32 TransmitColTimes; // when this is increase, at least
// one collision is found
UINT32 TransmitPTXTimes; // times of transmiting without error.
}STSTABOUTTMT;
// statistics
typedef struct
{
STSTABOUTRCV Rcv;
STSTABOUTTMT Tmt;
UINT32 CouterOverflowTimes; // tally counter full times.
UINT32 RemoteDMACompleteTimes; // remote DMA finish times.
UINT32 ShortBufferTimes; // how many time that encounter buffer shortage.
UINT32 ResetTimes; // how many time that the chip is reset.
UINT32 IPBufShortTimes; // TCP/IP could not provide buffers.
UINT32 VBBufShortTimes; // VB buffer could not be provided.
}STSTMAC;
// ether address of this interface card.
#define BED_ETHER_ADDR_AREA1 0x0
#define BED_ETHER_ADDR_AREA2 0x0
#define BED_ETHER_ADDR_AREA3 0x1b
#define BED_ETHER_ADDR_AREA4 0x18
#define BED_ETHER_ADDR_AREA5 0x22
#define BED_ETHER_ADDR_AREA6 0x02
// maximun lenth for a raw packet.
#define TRANSMIT_BUF_SIZE 1514 // MTU + 2 * address length + data length
#define RECEIVE_BUF_SIZE 1518 // MTU + 2 * address length + data length + CRC
#define TRANSMIT_BUF_MIN_SIZE 60
#define NET_TMO_MIIRST 100 // 100 ms to wait for MII reset.
#define NET_TMO_DMA 10 // 10 ms to wait for DMA.
#define NET_TMO_TMIT 20 // 20 ms to wait for transmit to be finished.
#define NET_TMO_LOOPWT 2000 // 2m to wait for loop response.
#define NET_NO_ERROR 0
#define NET_ERROR_MIIRST -1
#define NET_ERROR_PHYREAD -2
#define NET_ERROR_NE2REG -3
#define NET_ERROR_DMATMO -4
#define NET_ERROR_DMAERR -5
#define NET_ERROR_LOOPRSP -6
#define NET_ERROR_LOOPERR -7
#define NET_ERROR_MIIRD -8
#define NET_ERROR_PAKLEN -9
#define NET_ERROR_NOPAKIN -10
#define NET_ERROR_TRANSBLOCK -11
#define NET_PTL_TCPIP 1
#define NET_PTL_VIEWBEDCARE 2
#define NET_PTL_VIEWBEDNOTCARE 3
#define NET_PTL_NOONE 4
INT16 NU_Etopen (UCHAR *ether_addr, UINT16 irq_num,
UINT32 buff_addr, UINT32 base_addr);
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -