📄 test.h
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#define Enable_FPGA_UART4_Receiver { FPGAINTTYPE |= 0x41; *((UNCHAR *)FPGA_UART3_CR)=FPGAINTTYPE; }
#define Disable_FPGA_UART4_Receiver { FPGAINTTYPE &= 0xbe; *((UNCHAR *)FPGA_UART3_CR)=FPGAINTTYPE; }
#define FPGA_UART4_Transmitter_Buffer *((UNCHAR *)FPGA_UART3_DR)
#define Enable_FPGA_UART5_Transmitter { FPGAINTTYPE |= 0x82; *((UNCHAR *)FPGA_UART4_CR)=FPGAINTTYPE; }
#define Disable_FPGA_UART5_Transmitter { FPGAINTTYPE &= 0x7d; *((UNCHAR *)FPGA_UART4_CR)=FPGAINTTYPE; }
#define Enable_FPGA_UART5_Receiver { FPGAINTTYPE |= 0x41; *((UNCHAR *)FPGA_UART4_CR)=FPGAINTTYPE; }
#define Disable_FPGA_UART5_Receiver { FPGAINTTYPE &= 0xbe; *((UNCHAR *)FPGA_UART4_CR)=FPGAINTTYPE; }
#define FPGA_UART5_Transmitter_Buffer *((UNCHAR *)FPGA_UART4_DR)
#define Enable_FPGA_UART6_Transmitter { FPGAINTTYPE |= 0x82; *((UNCHAR *)FPGA_UART5_CR)=FPGAINTTYPE; }
#define Disable_FPGA_UART6_Transmitter { FPGAINTTYPE &= 0x7d; *((UNCHAR *)FPGA_UART5_CR)=FPGAINTTYPE; }
#define Enable_FPGA_UART6_Receiver { FPGAINTTYPE |= 0x41; *((UNCHAR *)FPGA_UART5_CR)=FPGAINTTYPE; }
#define Disable_FPGA_UART6_Receiver { FPGAINTTYPE &= 0xbe; *((UNCHAR *)FPGA_UART5_CR)=FPGAINTTYPE; }
#define FPGA_UART6_Transmitter_Buffer *((UNCHAR *)FPGA_UART5_DR)
#define Enable_FPGA_UART7_Transmitter { FPGAINTTYPE |= 0x82; *((UNCHAR *)FPGA_UART6_CR)=FPGAINTTYPE; }
#define Disable_FPGA_UART7_Transmitter { FPGAINTTYPE &= 0x7d; *((UNCHAR *)FPGA_UART6_CR)=FPGAINTTYPE; }
#define Enable_FPGA_UART7_Receiver { FPGAINTTYPE |= 0x41; *((UNCHAR *)FPGA_UART6_CR)=FPGAINTTYPE; }
#define Disable_FPGA_UART7_Receiver { FPGAINTTYPE &= 0xbe; *((UNCHAR *)FPGA_UART6_CR)=FPGAINTTYPE; }
#define FPGA_UART7_Transmitter_Buffer *((UNCHAR *)FPGA_UART6_DR)
#define Enable_FPGA_UART8_Transmitter { FPGAINTTYPE |= 0x82; *((UNCHAR *)FPGA_UART7_CR)=FPGAINTTYPE; }
#define Disable_FPGA_UART8_Transmitter { FPGAINTTYPE &= 0x7d; *((UNCHAR *)FPGA_UART7_CR)=FPGAINTTYPE; }
#define Enable_FPGA_UART8_Receiver { FPGAINTTYPE |= 0x41; *((UNCHAR *)FPGA_UART7_CR)=FPGAINTTYPE; }
#define Disable_FPGA_UART8_Receiver { FPGAINTTYPE &= 0xbe; *((UNCHAR *)FPGA_UART7_CR)=FPGAINTTYPE; }
#define FPGA_UART8_Transmitter_Buffer *((UNCHAR *)FPGA_UART7_DR)
//--------------------------end of serial IO----------------------------
//------------------MBUS data structure------------------------------------
// The length of three packet queue
#define RS5C372A_READ_PACKQUE_LEN (5)
#define RS5C372A_WRITE_PACKQUE_LEN (5)
#define X1203_READ_PACKQUE_LEN (5)
#define X1203_WRITE_PACKQUE_LEN (5)
#define PCF8591_READ_PACKQUE_LEN (10)
#define PCF8591_WRITE_PACKQUE_LEN (10)
#define CAT24C021_READ_PACKQUE_LEN (30)
#define CAT24C021_WRITE_PACKQUE_LEN (300)
#define TXDATA_LENGTH (16+4)
#define CAT24C021_READ_REPEAT 100
#define CAT24C021_WRITE_REPEAT 500
#define CAT24C021_SLAVE_ADDR 0xa0
#define PCF8591_SLAVE_ADDR 0x90
#define RS5C372A_SLAVE_ADDR 0x64
#define X1203_SLAVE_ADDR 0xde
#define X1203_CCR_ADDR1 0x0
#define X1203_CONTROL_REG 0x3f
#define X1203_RTCF 0x01
#define X1203_WEL 0x02
#define X1203_RWEL 0x04
#define X1203_24HOUR_SYSTEM 0x80
#define X1203_HOUR_PM 0x20
#define X1203_READ_REPEAT 20
#define X1203_WRITE_REPEAT 50
#define RS5C372A_READ_REPEAT 10
#define RS5C372A_WRITE_REPEAT 50
#define PCF8591_READ_REPEAT 5
#define PCF8591_WRITE_REPEAT 1
// RS5C372A register address define
#define RS5C372A_CONTROL_REG1 0x0e
#define RS5C372A_CONTROL_REG2 0x0f
// RS5C372A periodic interrupt cycle constant define.
#define RS5C372A_TIMER_SECOND 0x04
#define RS5C372A_TIMER_MINUTE 0x05
#define RS5C372A_TIMER_HOUR 0x06
#define RS5C372A_TIMER_MONTH 0x07
#define PCF8591_CONTROL_BYTE 0x45
// RS5C372A configuration constant define.
#define RS5C372A_12HOUR_SYSTEM 0x00
#define RS5C372A_24HOUR_SYSTEM 0x20
#define RS5C372A_XSTP 0x10
#define RS5C372A_ENABLE_TIMER 0x04
#define CAT24C021_PAGE_SIZE 16
#define PACKQUE_NUMBER 8
// operation mode constant define.
enum OPMode{OPMODE_QUERY, OPMODE_INTERRUPT};
enum OperationType{OP_WRITE = 0, OP_READ = 1};
// Real time clock chip type
//enum rtcType{RTC_NO, RTC_X1203, RTC_RS5C372A};
enum rtcType{RTC_NO, RTC_X1203, RTC_RS5C372A, RTC_DS1337};
/**
* MBUS communication protocol information struct.
*/
typedef struct{
// The number of byte being send first. this value must greater than 0
UNSHORT txLen1;
// The number of byte being send second. 0 if no data to be transmitted
// the second time, greater than 0 if there is some data to be transmitted
// the second time, and a RESTART signal must be sent before the sequence
// to be sent.
UNSHORT txLen2;
// The number of byte to be received. 0 if no data to be received.
UNSHORT rxLen;
// data to be transmitted. (including Slave address)
UNCHAR txData[TXDATA_LENGTH];
// The address for saving received data.
// Note: the saving routine will not check the range.
UNCHAR *rxData;
// Repeat transfer for how many times if transfer failed
UNSHORT repeatTimes;
}MBusPackType;
/**
* MBUS communication status information
*/
typedef struct{
// the operation mode of mbus: OPMODE_QUERY or OPMODE_INTERRUPT
UNCHAR mode;
// has current packet been processed: finished(1), not yet(0)
UNCHAR currPackFinished;
// Error count for no acknowledge, this variable will be increased by
// one every time MBUS module tramsnitted one byte but without acknowledge.
UNSHORT noAckError;
// Count for transfer failure, increase by one every time one packet was not
// transfered
UNSHORT transferFail;
// Real Time Clock chip type: X1203, RS5C372 or no
UNCHAR rtcChip;
// The packet being transfered
MBusPackType currPack;
}MBusInfoType;
static MBusInfoType sMBusInfo = {
OPMODE_QUERY, // initialize to query mode.
0, // current packet processing finished.
0, // error count clear
0, // clear transferFail
RTC_NO // No Real-Time Clock
};
/**
* MBUS communication protocol information manage struct. just a queue.
*/
typedef struct{
// write pointer.
UNSHORT getPtr;
// read pointer.
UNSHORT putPtr;
// the length of the queue
UNSHORT queueLen;
// the packet queue.
MBusPackType *packQue;
}MBusPackQueType;
typedef struct Stime {
SHORT year;
SHORT month;
SHORT date;
SHORT hour;
SHORT minute;
SHORT second;
} Stime ;
/**
* static variables define: Packet queues
*/
static MBusPackType sRS5C372AReadPack[RS5C372A_READ_PACKQUE_LEN];
static MBusPackType sRS5C372AWritePack[RS5C372A_WRITE_PACKQUE_LEN];
static MBusPackType sX1203ReadPack[X1203_READ_PACKQUE_LEN];
static MBusPackType sX1203WritePack[X1203_WRITE_PACKQUE_LEN];
static MBusPackType sPCF8591ReadPack[PCF8591_READ_PACKQUE_LEN];
static MBusPackType sPCF8591WritePack[PCF8591_WRITE_PACKQUE_LEN];
static MBusPackType sCAT24C021ReadPack[CAT24C021_READ_PACKQUE_LEN];
static MBusPackType sCAT24C021WritePack[CAT24C021_WRITE_PACKQUE_LEN];
////////////////////////////////////////////////////////////////////////////////
#define DS1337_READ_REPEAT 20
#define DS1337_WRITE_REPEAT 50
#define DS1337_SLAVE_ADDR 0xd0
#define DS1337_CONTROL_REG 0x0e
#define DS1337_SR_REG 0x0f
#define DS1337_OSF 0x80
#define DS1337_24HOUR_SYSTEM 0x40
#define DS1337_HOUR_PM 0x20
#define DS1337_SET_ADDR 0x00
#define DS1337_HEAD_INFO 0x02
#define DS1337_READ_PACKQUE_LEN (5)
#define DS1337_WRITE_PACKQUE_LEN (5)
static CHAR DS1337Initialize( VOID );
static CHAR DS1337WritePage(UCHAR baseAddr, UCHAR byteNum, UCHAR* data);
static CHAR DS1337ReadSeqByte(UCHAR baseAddr, UCHAR byteNum, UCHAR *dataAddr);
////////////////////////////////////////////////////////////////////////////////
/***************************************************************************/
void InitFpga( );
void iniramd ( char *clt);
void clrvram (void);
char vdeint();
void iniint();
void inics5();
void chacs5();
void randt3a();
void randt2a();
void randt2b();
void randt4a();
void randt4b();
void __TextOut( unsigned short x, unsigned short y, char color, char *text );
void __TextInv( unsigned short x, unsigned short y, char color, char *text );
void __TextCont( unsigned int x, char *text );
void __EcgHuge0_val( unsigned short x,unsigned short y,char *text );
void __OnePixel( unsigned short x,unsigned short y,char color);
void __HsLine( unsigned short hx1,unsigned short hy,unsigned short hx2,
char color);
void __VsLine( unsigned short vx,unsigned short vy1,unsigned short vy2,
char color);
void __DotLine( unsigned short x,unsigned short y,unsigned short w,
char color);
void __Xor_VsLine( unsigned short vx,unsigned short vy1,unsigned short vy2,
char color);
void __Rect( unsigned short x1,unsigned short y1,unsigned short x2,
unsigned short y2,char color);
void __Fblock( unsigned short x1,unsigned short y1,unsigned short x2,
unsigned short y2,char color);
void __Iblock( unsigned short x1,unsigned short y1,unsigned short x2,
unsigned short y2,char color);
void Test_Display( void );
//void Delay( SHORT delay_time );
void TestBuzzer(SHORT beep_time);
USHORT TestFlashRom(void);
void InitTimerInt();
void TimeInterupt();
void UART1Interrupt();
void UART1Test();
void FpgaInterupt();
SHORT FpgaTest();
VOID ReportFpgaTestResult( INT i, unsigned int test_result );
//-----------------------MBUS function---------------
SHORT TestMBusClock();
UNSHORT TestMBusEprom();
// function prototype define
VOID MBusInit(VOID);
//extern "C" VOID MBusMixedLisr(VOID);
VOID Mbus_Lisr(int vector);
//static INT16 ProcessNext(VOID);
static INT16 RepeatTransfer(VOID);
static VOID ConstructSequence(MBusPackType *pack);
static VOID StartTransfer(VOID);
static SHORT RepeatTransfer(void);
CHAR CAT24C021Initialize(VOID);
CHAR CAT24C021WritePage(UINT16 baseAddr, UINT16 byteNum, UCHAR *data);
CHAR CAT24C021WriteSeqByte(UINT16 baseAddr, UINT16 byteNum, UCHAR *data);
CHAR CAT24C021ReadSeqByte(UINT16 baseAddr, UINT16 byteNum, UCHAR *dataAddr);
static CHAR MBusTransferByQuery(MBusPackType *thePack);
static UCHAR WaitForMBusFree(VOID);
static UCHAR WaitForMIF(VOID);
static VOID UpdateCheckSum(UINT16 baseAddr, UINT16 byteNum, UCHAR *data);
static CHAR CAT24C021LoadMemoryMap(UCHAR *memoryMap);
CHAR CAT24C021WritePageWithCheck(UINT16 baseAddr, UINT16 byteNum, UCHAR *data);
CHAR CAT24C021WriteSeqByteWithCheck(UINT16 baseAddr, UINT16 byteNum, UCHAR *data);
INT IsMBusInQueryMode( VOID );
CHAR RTCInitialize(void);
static CHAR X1203WritePage(UNCHAR baseAddr, UNCHAR byteNum, UNCHAR* data);
static CHAR X1203ReadSeqByte(UNCHAR baseAddr, UNCHAR byteNum, UNCHAR *dataAddr);
static CHAR RS5C372AWriteSeqByte(UNCHAR baseAddr, UNCHAR byteNum, UNCHAR* data);
static CHAR RS5C372AReadSeqByte(UNCHAR baseAddr, UNCHAR byteNum, UNCHAR* data);
static CHAR RS5C372AInitialize( void );
CHAR RTCSetTime(Stime *theTime);
CHAR RTCReadTime(Stime *theTime);
//--------------------------end of MBUS function------------------------
//-------------START of FLASH DATA-----------------------------------
#define FLASH_BASE_ADDRESS 0x800000
//#define SIZE_OF_FLASH_ROM (0x100000 - 0x10000 ) //one mega - 64K bytes
#define SIZE_OF_FLASH_ROM (0x200000 - 0x20000 ) //2 mega - 128K bytes
#define END_OF_FLASH ( FLASH_BASE_ADDRESS + SIZE_OF_FLASH_ROM )
//#define SQC 0x00900000
//#define MBAR_ADDR 0x60000000
#define WRITE_READY 0x00800080
#define WRITE_OK 0x00100010
//flash ROM's maunufacturer code and device code
#define UNKNOWN_CHIP 0xaa
#define M_AMD 0x1
#define D_Am29F080 0xd5
#define D_Am29F800 0xd6
#define M_INTEL 0x00890089
#define D_PA28F800 0x88c088c0
#define PARRAPORT_PADDR (0x60000000 + 0x1c5)
#define PARRAPORT_PADAT (0x60000000 + 0x1c9)
typedef unsigned char UCHAR;
#define CHIP_PROTECT *((UCHAR *)PARRAPORT_PADAT) = 0xff; \
*((UCHAR *)PARRAPORT_PADDR) = 0x0f; \
*((UCHAR *)PARRAPORT_PADAT) = 0xfd;
#define CHIP_UNPROTECT *((UCHAR *)PARRAPORT_PADAT) = 0xff; \
*((UCHAR *)PARRAPORT_PADDR) = 0x0f; \
*((UCHAR *)PARRAPORT_PADAT) = 0xff;
//=====================8000 power board==============
#define BATTERY_STATUS (25*256/50)
#define LOW_DC (8.0*256/5/8)
//15V the AD sampled data is 15 / 8 *(256/5)
#define CHARGING_DC (15.0*256/5/8)
//10.3V the AD sampled data is 10.3 / 4 *(256/5)
#define LOW_BATTERY_VOLTAGE (10.3*256/5/4)
#define WARNING_BATTERY_VOLTAGE (10.9*256/5/4)
#define _8V_OF_12V_LINE ( 8 * 256 / 20 )
#define _16V_OF_12V_LINE ( 16 * 256 / 20 )
#define _10V_OF_12V_LINE ( 10 * 256 / 20 )
#define _15V_OF_12V_LINE ( 15 * 256 / 20 )
#define _11V_OF_12V_LINE ( 11 * 256 / 20 )
#define _14V_OF_12V_LINE ( 14 * 256 / 20 )
//attention please: 10_8V stand for 10.8V , 13_2V stand for 13.2V
#define _10_8V_OF_12V_LINE ( 10.8 * 256 / 20 )
#define _13_2V_OF_12V_LINE ( 13.2 * 256 / 20 )
typedef enum
{
ADC_ACDC,
ADC_BATT,
ADC_12V,
ADC_BATT_STATUS,
ADC_MAX
}AD_CHANNEL;
//---------------------------end of flash ram data-------------------
//extern unsigned int gCheckSum;
//extern unsigned int gPcInit;
//extern unsigned int gBootFileLen;
#endif⌨️ 快捷键说明
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