📄 test.h
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#ifndef __SLC_TEST_H__
#define __SLC_TEST_H__
#include "bastype.h"
#define DISP_CONTROL_REGISTER 0x600000 //显示控制寄存器
#define WAVE1_Y_DEFINE 0x600002 //波形1/2窗口垂直定位寄存器
#define WAVE2_Y_DEFINE 0x600004 //波形2/3窗口垂直定位寄存器
#define WAVE3_Y_DEFINE 0x600006 //波形3/4窗口垂直定位寄存器
#define WAVE4_Y_DEFINE 0x600008 //波形4/5窗口垂直定位寄存器
#define WAVE5_Y_DEFINE 0x60000a //波形5/6窗口垂直定位寄存器
#define WAVE6_Y_DEFINE 0x60000c //波形6/7窗口垂直定位寄存器
#define WAVE7_Y_DEFINE 0x60000e //波形7/8窗口垂直定位寄存器
#define WAVE1_X_DEFINE 0x600010 //波形1颜色与水平起点寄存器
#define WAVE2_X_DEFINE 0x600012 //波形2颜色与水平起点寄存器
#define WAVE3_X_DEFINE 0x600014 //波形3颜色与水平起点寄存器
#define WAVE4_X_DEFINE 0x600016 //波形4颜色与水平起点寄存器
#define WAVE5_X_DEFINE 0x600018 //波形5颜色与水平起点寄存器
#define WAVE6_X_DEFINE 0x60001a //波形6颜色与水平起点寄存器
#define WAVE7_X_DEFINE 0x60001c //波形7颜色与水平起点寄存器
#define WAVE8_X_DEFINE 0x60001e //波形8颜色与水平起点寄存器
#define WINDOW_REGISTER1 0x600020 //菜单窗口定位寄存器1（X1，Y1）
#define WINDOW_REGISTER2 0x600022 //菜单窗口定位寄存器2（X2，Y2）
#define VBUFFSIZE 240000 //字符屏缓冲区大小（按char计算）
#define WAVE_CLEAN_BUFSIZE 640 //波形清除缓冲区
#define MAXCOLOR 6 //波形最大色阶数
#define COLORINDEX 1 //波形颜色偏移量
#define WAVECOLOR 7 //波形颜色
#define SWEEP 0 //波形扫描方式
#define SCROLL 1 //波形滚动方式
#define TFT 0 //TFT显示器
#define CRT 1 //CRT显示器
#if defined(RESOLVING_800_600)
#define WAVE_SCN_HEIGHT 600 //波形屏高度
#define WAVE_SCN_WIDTH 560 //波形屏宽度
#define SCN_WIDTH 800 // 屏幕宽度
#define SCN_HEIGHT 600 // 屏幕高度
#else
#if defined(RESOLVING_640_480)
#define WAVE_SCN_HEIGHT 480 //波形屏高度
#define WAVE_SCN_WIDTH 560 //波形屏宽度
#define SCN_WIDTH 640 // 屏幕宽度
#define SCN_HEIGHT 480 // 屏幕高度
#endif
#endif
#define PHYWAVESCNWIDTH 320 //波形屏显存宽度（按字节计算）
#define WAVE_STARTX 4 //波形水平位置起点
typedef enum
{
BLACK,
LIGHTGRAY = 1,
GRAY = 2,
DARKGRAY = 3,
DARKESTGRAY = 4,
BLUE = 5,
//GRAY = DARKGRAY,
BLINKRED = 1,
BLINKGREEN = 2,
BLINKYELLOW = 3,
BLINKCYAN = 4,
BLINKWHITE = 5,
RED,
GREEN,
YELLOW,
CYAN,
WHITE,
DARKRED,
DARKGREEN,
DARKYELLOW,
DARKCYAN,
DARKWHITE,
COLOR_MAX
}COLOR;
#define RATE625 0
#define RATE125 1
#define RATE250 2
#define RATE500 3
#define MAX_PNUM625 20 // 6.25 mm/s
#define MAX_PNUM125 40 // 12.5 mm/s
#define MAX_PNUM250 80 // 25.0 mm/s
#define MAX_PNUM500 160 // 50.0 mm/s
// 各波形代号定义
#define ECG1WAVENO 0
#define ECG2WAVENO 1
#define ECG3WAVENO 2
#define ECG4WAVENO 3
#define ECG5WAVENO 4
#define ECG6WAVENO 5
#define ECG7WAVENO 6
#define IBP1WAVENO 7
#define IBP2WAVENO 8
#define IBP3WAVENO 9
#define IBP4WAVENO 10
#define RESPWAVENO 11
#define SPO2WAVENO 12
#define CO2WAVENO 13
#define WAVEOFF 14
#define CHNFONT_ADDRESS 0x990000 //中文16*16点阵字库地址
#define HUGEFONT 0 //40*60点阵参数数字字库
#define MEDIFONT 1 //24*34点阵参数数字字库
#define SMALLFONT 2 //16*16点阵参数数字字库
#define MICROFONT 3 //8*16点阵参数数字字库
#define MICROENGFONT 4 //8*8点阵英文字库
#define ENG24FONT 5 //24*24点阵初始化界面英文字库
#define CHN40FONT 6 //40*40点阵初始化界面中文字库
#define HUGE0HG 60 //42
#define MEDI2HG 34 //22
#define SMALL3HG 16
#define MICRO4HG 8
#define ENGMAXROW 16 //英文字符高度
//#define CHNMAXROW 16 //中文字符高度
#define CHNMAXROW 12 //中文字符高度
#define ASCMAXROW 8 //8*8点阵字符高度
typedef INT FONT;
/**************************************************************************/
#define MBAR_ADDR 0x60000000
#define TEST_RESULT_ADDR 0x3ff018
#define VPORT 0x00500000 //FPGA Initial Port & VRAM Base Address
#define RAMWA 0x00940000 //RAMDEC Write Address Register
#define RAMWD 0x00940002 //RAMDEC Data Register
#define RAMMK 0x00940004 //RAMDEC Pixel Mask Register
#define RAMTK 0x0094000C //RAMDEC TKD Register
#define RAMCD 0x0094000E //RAMDEC Command Register
#define SQC 0x00900000 //Display Mode Register
#define BLC 0x0090000A //Blink Controll Register
#define RTD3A 0x0090000C //UART 3A Data Registr
#define RTC3A 0x0090000E //UART 3A Command/status Register
#define RTD2A 0x00900010 //UART 2A Data Registr
#define RTC2A 0x00900012 //UART 2A Command/status Register
#define RTD2B 0x00900014 //UART 2B Data Registr
#define RTC2B 0x00900016 //UART 2B Command/status Register
#define RTD4A 0x00900018 //UART 4A Data Registr
#define RTC4A 0x0090001A //UART 4A Command/status Register
#define RTD4B 0x0090001C //UART 4B Data Registr
#define RTC4B 0x0090001E //UART 4B Command/status Register
#define IRQ5 0x00000074 //Display INT Vector Address
#define IRQ3 0x0000006C //UART 3 INT Vector Address
#define UOP0 0x6000017C //FPGA Done Status Port
#define UOP1 0x60000178 //FPGA Load Control Port
#define UOP2 0x600001BC //FPGA /INI Status Port
#define UOP3 0x600001B8 //FPGA /AC Control Port
#define FPGASTATE 0x60000174 //FPGA STATE REGISTER
//MCF5206 MBUS module registers address define
#define MADR (MBAR_ADDR + 0x1e0)
#define MFDR (MBAR_ADDR + 0x1e4)
#define MBCR (MBAR_ADDR + 0x1e8)
#define MBSR (MBAR_ADDR + 0x1ec)
#define MBDR (MBAR_ADDR + 0x1F0)
#define MBUS_ICR (MBAR_ADDR + 0x1e)
#define UART1_UOP1 (MBAR_ADDR + 0x1b8)
#define UART1_UOP0 (MBAR_ADDR + 0x1bc)
//#define PARALLEL_PORT (MBAR_ADDR + 0x1C9)
#define PARALLEL_PORT (MBAR_ADDR + 0x1B8)
#define POWER12V_PADDR (MBAR_ADDR + 0x1c5)
#define POWER12V_PADAT (MBAR_ADDR + 0x1c9)
void Delay( short delay_time );
//#define ENABLE_BACKLIGHT *((UNCHAR *)POWER12V_PADAT) = 0xff; \
// *((UNCHAR *)POWER12V_PADDR) = 0x04; \
// *((UNCHAR *)POWER12V_PADAT) = 0xfb;
#define ENABLE_BACKLIGHT *((UNCHAR *)POWER12V_PADAT) = 0xff; \
*((UNCHAR *)POWER12V_PADDR) = 0x0f; \
*((UNCHAR *)POWER12V_PADAT) = 0xff;
typedef short SHORT;
typedef unsigned short UNSHORT;
typedef unsigned short USHORT;
typedef char CHAR;
typedef unsigned char UCHAR;
typedef unsigned char UNCHAR;
//--------------------serial IO-------------------------------------
#define MBAR_ADDR 0x60000000
// 5206 system internal regesters
enum BUILDIN_SERIES_IO_REGESTERS
{
// read and write regesters
UMR11 = MBAR_ADDR + 0x140, // mode regester 1 for UART1,
UMR21 = MBAR_ADDR + 0x140, // mode regester 2 A, UART1,it share the same address with DUMR1A
UIVR1 = MBAR_ADDR + 0x170, // interrupt vector regester,for UART1
UMR12 = MBAR_ADDR + 0x180, // mode regester 1 B, for UART2
UMR22 = MBAR_ADDR + 0x180, // mode regester 2 B, for UART2,it share the same address with DUMR1B
UIVR2 = MBAR_ADDR + 0x1B0, // interrupt vector regester,for UART2
// read regesters
USR1 = MBAR_ADDR + 0x144, // status regester,for UART1
URB1 = MBAR_ADDR + 0x14c, // receiver buffer,for UART1
UIPCR1 = MBAR_ADDR + 0x150, // input port change regester,for UART1
UISR1 = MBAR_ADDR + 0x154, // interrupt status regester,for UART1
UIP1 = MBAR_ADDR + 0x174, // input port regester,for UART1
USR2 = MBAR_ADDR + 0x184, // status regester,for UART2
URB2 = MBAR_ADDR + 0x18c, // receiver buffer,for UART2
UIPCR2 = MBAR_ADDR + 0x190, // input port change regester,for UART2
UISR2 = MBAR_ADDR + 0x194, // interrupt status regester,for UART2
UIP2 = MBAR_ADDR + 0x1B4, // input port regester,for UART2
// write regesters
UCSR1 = MBAR_ADDR + 0x144, // clock-seect regester,for UART1
UCR1 = MBAR_ADDR + 0x148, // command regester,for UART1
UTB1 = MBAR_ADDR + 0x14c, // transmitter buffer,for UART1
UACR1 = MBAR_ADDR + 0x150, // auxiliary regester,for UART1
UIMR1 = MBAR_ADDR + 0x154, // interrupt mask regester,for UART1
UBG11 = MBAR_ADDR + 0x158, // Baud Rate Gennertor Prescale MSB,for UART1
UBG21 = MBAR_ADDR + 0x15C, // Baud Rate Gennertor Prescale LSB,for UART1
UCSR2 = MBAR_ADDR + 0x184, // clock-select regester,for UART2
UCR2 = MBAR_ADDR + 0x188, // command regester,for UART2
UTB2 = MBAR_ADDR + 0x18c, // transmitter buffer,for UART2
UACR2 = MBAR_ADDR + 0x190, // auxiliary regester,for UART2
UIMR2 = MBAR_ADDR + 0x194, // interrupt mask regester,for UART2
UBG12 = MBAR_ADDR + 0x198, // Baud Rate Gennertor Prescale MSB,for UART2
UBG22 = MBAR_ADDR + 0x19C, // Baud Rate Gennertor Prescale LSB,for UART2
IMR_ADDR = MBAR_ADDR + 0x36,
// read/write register
ICR_EXT1 = MBAR_ADDR + 0x14, // external IPL1 interrupt control register
ICR_EXT2 = MBAR_ADDR + 0x15, // external IPL2 interrupt control register
ICR_EXT3 = MBAR_ADDR + 0x16, // external IPL3 interrupt control register
ICR_EXT4 = MBAR_ADDR + 0x17, // external IPL4 interrupt control register
ICR_EXT5 = MBAR_ADDR + 0x18, // external IPL5 interrupt control register
ICR_EXT6 = MBAR_ADDR + 0x19, // external IPL6 interrupt control register
ICR_UART1 = MBAR_ADDR + 0x1f, // UART1 interrupt control register
ICR_UART2 = MBAR_ADDR + 0x20, // UART2 interrupt control register
TMR2 = MBAR_ADDR + 0x120, // Timer Mode Register for TIME2
TRR2 = MBAR_ADDR + 0x124 // Timer Reference Register for TIME2
};
// FPGA serial port regesters
enum SERIES_FPGA_REGESTERS
{
// 2A
FPGAUART2A_DATA_RCV = 0x900010,
FPGAUART2A_DATA_TRA = 0x900010,
FPGAUART2A_CMD = 0x900012,
FPGAUART2A_STATE = 0x900012,
// 2B
FPGAUART2B_DATA_RCV = 0x900014, // FPGA UART Receive Data Registr
FPGAUART2B_DATA_TRA = 0x900014, // FPGA UART Trasmmit Data Registr
FPGAUART2B_CMD = 0x900016, // FPGA UART Command Registr
FPGAUART2B_STATE = 0x900016, // FPGA UART Status Registr
// 3A
FPGAUART3A_DATA_RCV = 0x90000c,
FPGAUART3A_DATA_TRA = 0x90000c,
FPGAUART3A_CMD = 0x90000e,
FPGAUART3A_STATE = 0x90000e,
// 4A
FPGAUART4A_DATA_RCV = 0x900018,
FPGAUART4A_DATA_TRA = 0x900018,
FPGAUART4A_CMD = 0x90001a,
FPGAUART4A_STATE = 0x90001a,
// 4B
FPGAUART4B_DATA_RCV = 0x90001c,
FPGAUART4B_DATA_TRA = 0x90001c,
FPGAUART4B_CMD = 0x90001e,
FPGAUART4B_STATE = 0x90001e
};
#define FPGA_UART0_DR 0x00600040 //UART0 Data Registr
#define FPGA_UART0_CR 0x00600042 //UART0 Command/status Register
#define FPGA_UART0_BR 0x00600043 //UART0 baud rate Register(0~5: 4800,9600,19200,38400,57600,115200)
#define FPGA_UART1_DR 0x00600044 //UART1 Data Registr
#define FPGA_UART1_CR 0x00600046 //UART1 Command/status Register
#define FPGA_UART1_BR 0x00600047 //UART1 baud rate Register(0~5: 4800,9600,19200,38400,57600,115200)
#define FPGA_UART2_DR 0x00600048 //UART2 Data Registr
#define FPGA_UART2_CR 0x0060004a //UART2 Command/status Register
#define FPGA_UART2_BR 0x0060004b //UART2 baud rate Register(0~5: 4800,9600,19200,38400,57600,115200)
#define FPGA_UART3_DR 0x0060004c //UART3 Data Registr
#define FPGA_UART3_CR 0x0060004e //UART3 Command/status Register
#define FPGA_UART3_BR 0x0060004f //UART3 baud rate Register(0~5: 4800,9600,19200,38400,57600,115200)
#define FPGA_UART4_DR 0x00600050 //UART4 Data Registr
#define FPGA_UART4_CR 0x00600052 //UART4 Command/status Register
#define FPGA_UART4_BR 0x00600053 //UART4 baud rate Register(0~5: 4800,9600,19200,38400,57600,115200)
#define FPGA_UART5_DR 0x00600054 //UART5 Data Registr
#define FPGA_UART5_CR 0x00600056 //UART5 Command/status Register
#define FPGA_UART5_BR 0x00600057 //UART5 baud rate Register(0~5: 4800,9600,19200,38400,57600,115200)
#define FPGA_UART6_DR 0x00600058 //UART6 Data Registr
#define FPGA_UART6_CR 0x0060005a //UART6 Command/status Register
#define FPGA_UART6_BR 0x0060005b //UART6 baud rate Register(0~5: 4800,9600,19200,38400,57600,115200)
#define FPGA_UART7_DR 0x0060005c //UART7 Data Registr
#define FPGA_UART7_CR 0x0060005e //UART7 Command/status Register
#define FPGA_UART7_BR 0x0060005f //UART7 baud rate Register(0~5: 4800,9600,19200,38400,57600,115200)
#define STATUS_RXRDY 0x80
#define STATUS_FRAME_ERR 0x40
#define STATUS_OVERRUN_ERR 0x20
#define STATUS_PARITY_ERR 0x10
#define STATUS_TXRDY 0x08
#define PARITY_EVEN_SET 0x0c
#define PARITY_ODD_SET 0x08
#define NO_PARITY_SET 0x04
#define Enable_UART1_Transmitter *((UNCHAR *) UCR1) = 0x04 // UART1
#define Disable_UART1_Transmitter *((UNCHAR *) UCR1) = 0x08
#define Enable_UART1_Receiver *((UNCHAR *) UCR1) = 0x01
#define Disable_UART1_Receiver *((UNCHAR *) UCR1) = 0x02
#define UART1_Transmitter_Buffer *((UNCHAR *) UTB1)
#define Enable_UART2_Transmitter *((UNCHAR *) UCR2) = 0x04 // UART2
#define Disable_UART2_Transmitter *((UNCHAR *) UCR2) = 0x08
#define Enable_UART2_Receiver *((UNCHAR *) UCR2) = 0x01
#define Disable_UART2_Receiver *((UNCHAR *) UCR2) = 0x02
#define UART2_Transmitter_Buffer *((UNCHAR *) UTB2)
#define Enable_FPGA_UART1_Transmitter { FPGAINTTYPE |= 0x82; *((UNCHAR *)FPGA_UART0_CR)=FPGAINTTYPE; }
#define Disable_FPGA_UART1_Transmitter { FPGAINTTYPE &= 0x7d; *((UNCHAR *)FPGA_UART0_CR)=FPGAINTTYPE; }
#define Enable_FPGA_UART1_Receiver { FPGAINTTYPE |= 0x41; *((UNCHAR *)FPGA_UART0_CR)=FPGAINTTYPE; }
#define Disable_FPGA_UART1_Receiver { FPGAINTTYPE &= 0xbe; *((UNCHAR *)FPGA_UART0_CR)=FPGAINTTYPE; }
#define FPGA_UART1_Transmitter_Buffer *((UNCHAR *)FPGA_UART0_DR)
#define Enable_FPGA_UART2_Transmitter { FPGAINTTYPE |= 0x82; *((UNCHAR *)FPGA_UART1_CR)=FPGAINTTYPE; }
#define Disable_FPGA_UART2_Transmitter { FPGAINTTYPE &= 0x7d; *((UNCHAR *)FPGA_UART1_CR)=FPGAINTTYPE; }
#define Enable_FPGA_UART2_Receiver { FPGAINTTYPE |= 0x41; *((UNCHAR *)FPGA_UART1_CR)=FPGAINTTYPE; }
#define Disable_FPGA_UART2_Receiver { FPGAINTTYPE &= 0xbe; *((UNCHAR *)FPGA_UART1_CR)=FPGAINTTYPE; }
#define FPGA_UART2_Transmitter_Buffer *((UNCHAR *)FPGA_UART1_DR)
#define Enable_FPGA_UART3_Transmitter { FPGAINTTYPE |= 0x82; *((UNCHAR *)FPGA_UART2_CR)=FPGAINTTYPE; }
#define Disable_FPGA_UART3_Transmitter { FPGAINTTYPE &= 0x7d; *((UNCHAR *)FPGA_UART2_CR)=FPGAINTTYPE; }
#define Enable_FPGA_UART3_Receiver { FPGAINTTYPE |= 0x41; *((UNCHAR *)FPGA_UART2_CR)=FPGAINTTYPE; }
#define Disable_FPGA_UART3_Receiver { FPGAINTTYPE &= 0xbe; *((UNCHAR *)FPGA_UART2_CR)=FPGAINTTYPE; }
#define FPGA_UART3_Transmitter_Buffer *((UNCHAR *)FPGA_UART2_DR)
#define Enable_FPGA_UART4_Transmitter { FPGAINTTYPE |= 0x82; *((UNCHAR *)FPGA_UART3_CR)=FPGAINTTYPE; }
#define Disable_FPGA_UART4_Transmitter { FPGAINTTYPE &= 0x7d; *((UNCHAR *)FPGA_UART3_CR)=FPGAINTTYPE; }
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