uartdrv.cpp

coldfire5206芯片的boot程序

/*
FileName:      uartdrv.cpp
Description:   The common variables and interfaces for all UARTs.
Version:       v1.0
Function List:
ClearUartForModule

History:
<author>           <time>                <desc>
Li Linghua        2001/5/25            The file was created today.
li Linghua        2001/11/06           modify DummyUartInfo's initialization data. 
shiliangcai		2002/10/31			 modify for predigesting version control
*/


#include  "bastype.h"
#include  "mcf5206.h"
//#include  "fpgauart.h"
#include  "fpga.h"
#include  "uart1.h"
#include  "uart2.h"
#include "flash.h"
#include "main.h"
#include  "uartdrv.h"

static const UCHAR FPGA_UART_BAUD_RATE[BR_MAX] =
{
	0x07, // 2400 BPS
	0x06, // 4800 BPS
	0x05, // 9600 BPS
	0x04, // 19200 BPS
	0x03, // 38400 BPS
	0x02, // 57600 BPS
	0x01, // 76800 BPS
	0x00 // 115200 BPS
};

// UART status constant define
#define  FPGA_UART_STATUS_RXRDY       0x80
#define  FPGA_UART_STATUS_TXRDY       0x08

#define  FPGA_UART_STATUS_FRAME_ERR   0x40
#define  FPGA_UART_STATUS_OVERRUN_ERR 0x20
#define  FPGA_UART_STATUS_PARITY_ERR  0x10


#define  FPGA_UART_PARITY_EVEN_SET  0x0c
#define  FPGA_UART_PARITY_ODD_SET   0x08
#define  FPGA_UART_NO_PARITY_SET    0x00

#define  FPGA_UART_HAS_PARITY       0x08

///////////////////////////////////////////////////////////////////////////////////////////
// the table which uart's IMR is mapped -------------start
// 注意 这里定义的是8000/9000的，6000的FPGA 串口3应该为MCF5206::IM_EINT2，
// 在函数ConfigUart()中修正
UINT32 g_alUartIMRTable[10] = 	// 串口中断号    含义
{
	MCF5206::IM_UART1,		//	0x00      CPU 串口0
		MCF5206::IM_UART2,		//	0x01      CPU 串口1
		MCF5206::IM_EINT2,		//	0x03      FPGA 串口0
		MCF5206::IM_EINT2,		//	0x04      FPGA 串口1
		MCF5206::IM_EINT2,		//	0x05      FPGA 串口2
		MCF5206::IM_EINT3,		//	0x06      FPGA 串口3
		MCF5206::IM_EINT3,		//	0x07      FPGA 串口4
		MCF5206::IM_EINT3,		//	0x08      FPGA 串口5
		MCF5206::IM_EINT3,		//	0x09      FPGA 串口6
		MCF5206::IM_EINT3		//	0x0A      FPGA 串口7
};
// the table which uart's IMR is mapped ------------- end
///////////////////////////////////////////////////////////////////////////////////////////


////////////////////////////////////////////////////////////////////////////////
// Uart1 and Uart2's const for config setting ------ start
// Bus Clock Frequency is 54MHz
UCHAR sUBG1Const[BR_MAX] =
{
	0x02, // 2400 BPS
		0x01, // 4800 BPS
		0x00, // 9600 BPS
		0x00, // 19200 BPS
		0x00, // 38400 BPS
		0x00, // 57600 BPS
		0x00, // 76800 BPS
		0x00, // 115200 BPS
};
UCHAR sUBG2Const[BR_MAX] =
{
	0xbf, // 2400 BPS
		0x5f, // 4800 BPS
		0xb0, // 9600 BPS
		0x58, // 19200 BPS
		0x2c, // 38400 BPS
		0x1d, // 57600 BPS
		0x16, // 76800 BPS
		0x0e, // 115200 BPS
};

UCHAR sParityConst[PARITY_MAX] =
{
	0x04, // PARITY_ODD,
		0x00, // PARITY_EVEN,
		0x10, // PARITY_NO,
		0x18  // PARITY_MULTIDROP,
};

UCHAR sDataBitsConst[DATABITS_MAX] =
{
	0x00, // 5,
		0x01, // 6,
		0x02, // 7,
		0x03  // 8,
};

UCHAR sStopBitsConst[STOPBITS_MAX] =
{
	0x07, // 1
		0x08  // 1.563
};
// Uart1 and Uart2's const for config setting ------ end
////////////////////////////////////////////////////////////////////////////////

#define FPGA_UART_COUNT 8

FPGAUARTALLINFO gFpgaUartInfoTable[FPGA_UART_COUNT];

void ConfigUart()
{
	if (g_stSysFlag.stFSysFlag.ucFlashCircuitType == FLASH_CIRCUIT_VER_6000)
	{
		g_alUartIMRTable[5] = MCF5206::IM_EINT2;
	}
	// 参见 FPGA.H
	UCHAR* p_reg_addr = (UCHAR*)FPGA_UART0_DR;
	for (int i = 0; i < FPGA_UART_COUNT; i ++)
	{
		gFpgaUartInfoTable[i].dr = p_reg_addr;
		p_reg_addr += 2;
		gFpgaUartInfoTable[i].cr = p_reg_addr;
		p_reg_addr ++;
		gFpgaUartInfoTable[i].br = p_reg_addr;
		p_reg_addr ++;
	}

	return;
}

BOOL InitUart(UCHAR uart_id, const UARTCONFIG* config, UCHAR enable_tx, UCHAR enable_rx)
{
	if (uart_id >= UART_MAX)
	{
		return FALSE;
	}

	if (uart_id == CPU_UART_1)
	{
		CF5206Uart1SetConfig(config);
		CF5206Uart1Reset();
		CF5206Uart1ReceiveControl(enable_rx);
		CF5206Uart1TransmitControl(enable_tx);
	}
	else if (uart_id == CPU_UART_2)
	{
		CF5206Uart2SetConfig(config);
		CF5206Uart2Reset();
		CF5206Uart2ReceiveControl(enable_rx);
		CF5206Uart2TransmitControl(enable_tx);
	}
	else
	{
		FpgaUartSetConfig( uart_id - FPGA_UART_0, config);
		FpgaUartReset( uart_id - FPGA_UART_0 );
		FpgaUartReceiveControl( uart_id - FPGA_UART_0, enable_rx );
		FpgaUartTransmitControl( uart_id - FPGA_UART_0, enable_tx );
	}

	return TRUE;
}

INT16 UartWriteString(UCHAR uart_id, UCHAR* string, UINT16 str_len)
{
	int len;

	if (uart_id >= UART_MAX)
	{
		return 0;
	}

	if (uart_id == CPU_UART_1)
	{
		len = CF5206Uart1WriteString(string, str_len);
	}
	else if (uart_id == CPU_UART_2)
	{
		len = CF5206Uart2WriteString(string, str_len);
	}
	else
	{
		len = FpgaUartWriteString(uart_id - FPGA_UART_0, string, str_len);
	}

	return len;
}

INT16 UartReadString(UCHAR uart_id, UCHAR* string, UINT16 str_len)
{
	int len;
	if (uart_id >= UART_MAX)
	{
		return 0;
	}

	if (uart_id == CPU_UART_1)
	{
		len = CF5206Uart1ReadString(string, str_len);
	}
	else if (uart_id == CPU_UART_2)
	{
		len = CF5206Uart2ReadString(string, str_len);
	}
	else
	{
		len = FpgaUartReadString(uart_id - FPGA_UART_0, string, str_len);
	}

	return len;
}


/*
Function Name:  FpgaUartSetConfig
Description:    Using given configuration to initialize UART
Parameters:     config -- configuration data
Return:         Nothing
Output:         Nothing
Test&Revision:  Done
*/
VOID  FpgaUartSetConfig( UINT16 fpga_uart_index, const UARTCONFIG* config)
{
	FPGAUARTALLINFO& uart_all_info = gFpgaUartInfoTable[fpga_uart_index];

	switch (config->parity)
	{
	case PARITY_ODD:  uart_all_info.set = FPGA_UART_PARITY_ODD_SET; break;

	case PARITY_EVEN: uart_all_info.set = FPGA_UART_PARITY_EVEN_SET; break;

	default:   uart_all_info.set = FPGA_UART_NO_PARITY_SET; break;
	}

	*(uart_all_info.cr) = uart_all_info.set;

	// baud rate set
	*(uart_all_info.br) = FPGA_UART_BAUD_RATE[config->baudRate];

}


/*
Function Name:  FpgaUartReset
Description:    reset UART's buffer and status
Parameters:     No
Return:         Nothing
Output:         Nothing
Test&Revision:  Done
*/
VOID  FpgaUartReset( UINT16 fpga_uart_index )
{
	FPGAUARTALLINFO& uart_all_info = gFpgaUartInfoTable[fpga_uart_index];

	// reset buffer pointer
	uart_all_info.receiveBufHead = uart_all_info.receiveBuffer;
	uart_all_info.receiveBufTail = uart_all_info.receiveBuffer + RECEIVE_BUF_LENGTH - 1;

	uart_all_info.transmitBufHead = uart_all_info.transmitBuffer;
	uart_all_info.transmitBufTail = uart_all_info.transmitBuffer + TRANSMIT_BUF_LENGTH - 1;

	uart_all_info.receiveInPtr   = uart_all_info.receiveBufHead;
	uart_all_info.receiveOutPtr  = uart_all_info.receiveBufHead;
	uart_all_info.transmitInPtr  = uart_all_info.transmitBufHead;
	uart_all_info.transmitOutPtr = uart_all_info.transmitBufHead;

	// reset status
	uart_all_info.receivedBytes    = 0;
	uart_all_info.isTxBufferEmpty  = TRUE;

	// reset error counter
	uart_all_info.parityError = 0;
	uart_all_info.overRunError = 0;
	uart_all_info.frameError = 0;
}


/*
Function Name:  FpgaUartWriteString
Description:    Transmit a string from UART
Parameters:     string  --  the characters to be transmited
str_len --  the number of characters of the string
Return:         bytes transmitted
Output:         Nothing
Test&Revision:  Done
1. 2001.7.27: if no enough buffer, no byte will be transmitted,